[AArch64][SVE] Asm: Support for vector element compares.

This patch adds instructions for comparing elements from two vectors, e.g.
  cmpgt p0.s, p0/z, z0.s, z1.s

and also adds support for comparing to a 64-bit wide element vector, e.g.
  cmpgt p0.s, p0/z, z0.s, z1.d

The patch also contains aliases for certain comparisons, e.g.:
  cmple p0.s, p0/z, z0.s, z1.s => cmpge p0.s, p0/z, z1.s, z0.s
  cmplo p0.s, p0/z, z0.s, z1.s => cmphi p0.s, p0/z, z1.s, z0.s
  cmpls p0.s, p0/z, z0.s, z1.s => cmphs p0.s, p0/z, z1.s, z0.s
  cmplt p0.s, p0/z, z0.s, z1.s => cmpgt p0.s, p0/z, z1.s, z0.s

llvm-svn: 334931

22 files changed, 1228 insertions, 0 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 2f9defd2688..8ff5cd2163a 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -509,6 +509,24 @@ let Predicates = [HasSVE] in {
   defm INCD_XPiI : sve_int_pred_pattern_a<0b110, "incd">;
   defm DECD_XPiI : sve_int_pred_pattern_a<0b111, "decd">;
 
+  defm CMPHS_PPzZZ : sve_int_cmp_0<0b000, "cmphs">;
+  defm CMPHI_PPzZZ : sve_int_cmp_0<0b001, "cmphi">;
+  defm CMPGE_PPzZZ : sve_int_cmp_0<0b100, "cmpge">;
+  defm CMPGT_PPzZZ : sve_int_cmp_0<0b101, "cmpgt">;
+  defm CMPEQ_PPzZZ : sve_int_cmp_0<0b110, "cmpeq">;
+  defm CMPNE_PPzZZ : sve_int_cmp_0<0b111, "cmpne">;
+
+  defm CMPEQ_WIDE_PPzZZ : sve_int_cmp_0_wide<0b010, "cmpeq">;
+  defm CMPNE_WIDE_PPzZZ : sve_int_cmp_0_wide<0b011, "cmpne">;
+  defm CMPGE_WIDE_PPzZZ : sve_int_cmp_1_wide<0b000, "cmpge">;
+  defm CMPGT_WIDE_PPzZZ : sve_int_cmp_1_wide<0b001, "cmpgt">;
+  defm CMPLT_WIDE_PPzZZ : sve_int_cmp_1_wide<0b010, "cmplt">;
+  defm CMPLE_WIDE_PPzZZ : sve_int_cmp_1_wide<0b011, "cmple">;
+  defm CMPHS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b100, "cmphs">;
+  defm CMPHI_WIDE_PPzZZ : sve_int_cmp_1_wide<0b101, "cmphi">;
+  defm CMPLO_WIDE_PPzZZ : sve_int_cmp_1_wide<0b110, "cmplo">;
+  defm CMPLS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b111, "cmpls">;
+
   defm INDEX_RR : sve_int_index_rr<"index">;
   defm INDEX_IR : sve_int_index_ir<"index">;
   defm INDEX_RI : sve_int_index_ri<"index">;
@@ -540,4 +558,40 @@ let Predicates = [HasSVE] in {
 
   def : InstAlias<"nots $Pd, $Pg/z, $Pn",
                   (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg), 1>;
+
+  def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
+                  (CMPGE_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
+  def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
+                  (CMPGE_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+  def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
+                  (CMPGE_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+  def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
+                  (CMPGE_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+
+  def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
+                  (CMPHI_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
+  def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
+                  (CMPHI_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+  def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
+                  (CMPHI_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+  def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
+                  (CMPHI_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+
+  def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
+                  (CMPHS_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
+  def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
+                  (CMPHS_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+  def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
+                  (CMPHS_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+  def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
+                  (CMPHS_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+
+  def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
+                  (CMPGT_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
+  def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
+                  (CMPGT_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+  def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
+                  (CMPGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+  def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
+                  (CMPGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
 }
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 5d39ecf8b50..f4a63bb1a71 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -950,6 +950,54 @@ multiclass sve_int_dup_imm_pred_zero<string asm> {
 }
 
 //===----------------------------------------------------------------------===//
+// SVE Integer Compare - Vectors Group
+//===----------------------------------------------------------------------===//
+
+class sve_int_cmp<bit cmp_1, bits<2> sz8_64, bits<3> opc, string asm,
+                  PPRRegOp pprty, ZPRRegOp zprty1, ZPRRegOp zprty2>
+: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty1:$Zn, zprty2:$Zm),
+  asm, "\t$Pd, $Pg/z, $Zn, $Zm",
+  "",
+  []>, Sched<[]> {
+  bits<4> Pd;
+  bits<3> Pg;
+  bits<5> Zm;
+  bits<5> Zn;
+  let Inst{31-24} = 0b00100100;
+  let Inst{23-22} = sz8_64;
+  let Inst{21}    = 0b0;
+  let Inst{20-16} = Zm;
+  let Inst{15}    = opc{2};
+  let Inst{14}    = cmp_1;
+  let Inst{13}    = opc{1};
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Zn;
+  let Inst{4}     = opc{0};
+  let Inst{3-0}   = Pd;
+
+  let Defs = [NZCV];
+}
+
+multiclass sve_int_cmp_0<bits<3> opc, string asm> {
+  def _B : sve_int_cmp<0b0, 0b00, opc, asm, PPR8, ZPR8, ZPR8>;
+  def _H : sve_int_cmp<0b0, 0b01, opc, asm, PPR16, ZPR16, ZPR16>;
+  def _S : sve_int_cmp<0b0, 0b10, opc, asm, PPR32, ZPR32, ZPR32>;
+  def _D : sve_int_cmp<0b0, 0b11, opc, asm, PPR64, ZPR64, ZPR64>;
+}
+
+multiclass sve_int_cmp_0_wide<bits<3> opc, string asm> {
+  def _B : sve_int_cmp<0b0, 0b00, opc, asm, PPR8, ZPR8, ZPR64>;
+  def _H : sve_int_cmp<0b0, 0b01, opc, asm, PPR16, ZPR16, ZPR64>;
+  def _S : sve_int_cmp<0b0, 0b10, opc, asm, PPR32, ZPR32, ZPR64>;
+}
+
+multiclass sve_int_cmp_1_wide<bits<3> opc, string asm> {
+  def _B : sve_int_cmp<0b1, 0b00, opc, asm, PPR8, ZPR8, ZPR64>;
+  def _H : sve_int_cmp<0b1, 0b01, opc, asm, PPR16, ZPR16, ZPR64>;
+  def _S : sve_int_cmp<0b1, 0b10, opc, asm, PPR32, ZPR32, ZPR64>;
+}
+
+//===----------------------------------------------------------------------===//
 //SVE Index Generation Group
 //===----------------------------------------------------------------------===//
 
diff --git a/llvm/test/MC/AArch64/SVE/cmpeq-diagnostics.s b/llvm/test/MC/AArch64/SVE/cmpeq-diagnostics.s
new file mode 100644
index 00000000000..4901f1a44ba
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmpeq-diagnostics.s
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Restricted predicate out of range.
+
+cmpeq p0.b, p8/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: cmpeq p0.b, p8/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate operation
+
+cmpeq p0.b, p0/m, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: cmpeq p0.b, p0/m, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid source registers
+
+cmpeq p0.b, p0/z, z0.b, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpeq p0.h, p0/z, z0.h, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpeq p0.s, p0/z, z0.s, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpeq p0.d, p0/z, z0.d, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpeq p0.b, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpeq p0.b, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpeq p0.h, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpeq p0.h, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpeq p0.s, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpeq p0.s, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpeq p0.d, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpeq p0.d, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/cmpeq.s b/llvm/test/MC/AArch64/SVE/cmpeq.s
new file mode 100644
index 00000000000..f5511d76eac
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmpeq.s
@@ -0,0 +1,51 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+cmpeq   p0.b, p0/z, z0.b, z0.b
+// CHECK-INST: cmpeq p0.b, p0/z, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0xa0,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 00 24 <unknown>
+
+cmpeq   p0.h, p0/z, z0.h, z0.h
+// CHECK-INST: cmpeq p0.h, p0/z, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 40 24 <unknown>
+
+cmpeq   p0.s, p0/z, z0.s, z0.s
+// CHECK-INST: cmpeq p0.s, p0/z, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0xa0,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 80 24 <unknown>
+
+cmpeq   p0.d, p0/z, z0.d, z0.d
+// CHECK-INST: cmpeq p0.d, p0/z, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0xa0,0xc0,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 c0 24 <unknown>
+
+cmpeq   p0.b, p0/z, z0.b, z0.d
+// CHECK-INST: cmpeq p0.b, p0/z, z0.b, z0.d
+// CHECK-ENCODING: [0x00,0x20,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 00 24 <unknown>
+
+cmpeq   p0.h, p0/z, z0.h, z0.d
+// CHECK-INST: cmpeq p0.h, p0/z, z0.h, z0.d
+// CHECK-ENCODING: [0x00,0x20,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 40 24 <unknown>
+
+cmpeq   p0.s, p0/z, z0.s, z0.d
+// CHECK-INST: cmpeq p0.s, p0/z, z0.s, z0.d
+// CHECK-ENCODING: [0x00,0x20,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 20 80 24 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/cmpge-diagnostics.s b/llvm/test/MC/AArch64/SVE/cmpge-diagnostics.s
new file mode 100644
index 00000000000..bae3eb599b5
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmpge-diagnostics.s
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Restricted predicate out of range.
+
+cmpge p0.b, p8/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: cmpge p0.b, p8/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate operation
+
+cmpge p0.b, p0/m, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: cmpge p0.b, p0/m, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid source registers
+
+cmpge p0.b, p0/z, z0.b, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpge p0.b, p0/z, z0.b, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpge p0.h, p0/z, z0.h, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpge p0.h, p0/z, z0.h, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpge p0.s, p0/z, z0.s, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpge p0.s, p0/z, z0.s, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpge p0.d, p0/z, z0.d, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpge p0.d, p0/z, z0.d, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpge p0.b, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpge p0.b, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpge p0.h, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpge p0.h, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpge p0.s, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpge p0.s, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpge p0.d, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpge p0.d, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/cmpge.s b/llvm/test/MC/AArch64/SVE/cmpge.s
new file mode 100644
index 00000000000..f9eb9b9c9f3
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmpge.s
@@ -0,0 +1,50 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+cmpge   p0.b, p0/z, z0.b, z0.b
+// CHECK-INST: cmpge   p0.b, p0/z, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0x80,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 00 24 <unknown>
+
+cmpge   p0.h, p0/z, z0.h, z0.h
+// CHECK-INST: cmpge   p0.h, p0/z, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x80,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 40 24 <unknown>
+
+cmpge   p0.s, p0/z, z0.s, z0.s
+// CHECK-INST: cmpge   p0.s, p0/z, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0x80,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 80 24 <unknown>
+
+cmpge   p0.d, p0/z, z0.d, z0.d
+// CHECK-INST: cmpge   p0.d, p0/z, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x80,0xc0,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 c0 24 <unknown>
+
+cmpge   p0.b, p0/z, z0.b, z0.d
+// CHECK-INST: cmpge   p0.b, p0/z, z0.b, z0.d
+// CHECK-ENCODING: [0x00,0x40,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 00 24 <unknown>
+
+cmpge   p0.h, p0/z, z0.h, z0.d
+// CHECK-INST: cmpge   p0.h, p0/z, z0.h, z0.d
+// CHECK-ENCODING: [0x00,0x40,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 40 24 <unknown>
+
+cmpge   p0.s, p0/z, z0.s, z0.d
+// CHECK-INST: cmpge   p0.s, p0/z, z0.s, z0.d
+// CHECK-ENCODING: [0x00,0x40,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 40 80 24 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/cmpgt-diagnostics.s b/llvm/test/MC/AArch64/SVE/cmpgt-diagnostics.s
new file mode 100644
index 00000000000..71f46637fbd
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmpgt-diagnostics.s
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Restricted predicate out of range.
+
+cmpgt p0.b, p8/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: cmpgt p0.b, p8/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate operation
+
+cmpgt p0.b, p0/m, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: cmpgt p0.b, p0/m, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid source registers
+
+cmpgt p0.b, p0/z, z0.b, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpgt p0.b, p0/z, z0.b, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpgt p0.h, p0/z, z0.h, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpgt p0.h, p0/z, z0.h, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpgt p0.s, p0/z, z0.s, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpgt p0.d, p0/z, z0.d, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpgt p0.d, p0/z, z0.d, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpgt p0.b, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpgt p0.b, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpgt p0.h, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpgt p0.h, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpgt p0.s, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpgt p0.s, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpgt p0.d, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpgt p0.d, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/cmpgt.s b/llvm/test/MC/AArch64/SVE/cmpgt.s
new file mode 100644
index 00000000000..edc7c7e2baa
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmpgt.s
@@ -0,0 +1,51 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+cmpgt   p0.b, p0/z, z0.b, z0.b
+// CHECK-INST: cmpgt p0.b, p0/z, z0.b, z0.b
+// CHECK-ENCODING: [0x10,0x80,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 80 00 24 <unknown>
+
+cmpgt   p0.h, p0/z, z0.h, z0.h
+// CHECK-INST: cmpgt p0.h, p0/z, z0.h, z0.h
+// CHECK-ENCODING: [0x10,0x80,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 80 40 24 <unknown>
+
+cmpgt   p0.s, p0/z, z0.s, z0.s
+// CHECK-INST: cmpgt p0.s, p0/z, z0.s, z0.s
+// CHECK-ENCODING: [0x10,0x80,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 80 80 24 <unknown>
+
+cmpgt   p0.d, p0/z, z0.d, z0.d
+// CHECK-INST: cmpgt p0.d, p0/z, z0.d, z0.d
+// CHECK-ENCODING: [0x10,0x80,0xc0,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 80 c0 24 <unknown>
+
+cmpgt   p0.b, p0/z, z0.b, z0.d
+// CHECK-INST: cmpgt p0.b, p0/z, z0.b, z0.d
+// CHECK-ENCODING: [0x10,0x40,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 40 00 24 <unknown>
+
+cmpgt   p0.h, p0/z, z0.h, z0.d
+// CHECK-INST: cmpgt p0.h, p0/z, z0.h, z0.d
+// CHECK-ENCODING: [0x10,0x40,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 40 40 24 <unknown>
+
+cmpgt   p0.s, p0/z, z0.s, z0.d
+// CHECK-INST: cmpgt p0.s, p0/z, z0.s, z0.d
+// CHECK-ENCODING: [0x10,0x40,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 40 80 24 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/cmphi-diagnostics.s b/llvm/test/MC/AArch64/SVE/cmphi-diagnostics.s
new file mode 100644
index 00000000000..f27490ebebe
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmphi-diagnostics.s
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Restricted predicate out of range.
+
+cmphi p0.b, p8/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: cmphi p0.b, p8/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate operation
+
+cmphi p0.b, p0/m, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: cmphi p0.b, p0/m, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid source registers
+
+cmphi p0.b, p0/z, z0.b, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmphi p0.b, p0/z, z0.b, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmphi p0.h, p0/z, z0.h, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmphi p0.h, p0/z, z0.h, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmphi p0.s, p0/z, z0.s, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmphi p0.s, p0/z, z0.s, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmphi p0.d, p0/z, z0.d, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmphi p0.d, p0/z, z0.d, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmphi p0.b, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmphi p0.b, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmphi p0.h, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmphi p0.h, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmphi p0.s, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmphi p0.s, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmphi p0.d, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmphi p0.d, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/cmphi.s b/llvm/test/MC/AArch64/SVE/cmphi.s
new file mode 100644
index 00000000000..c0afa62c33e
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmphi.s
@@ -0,0 +1,51 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+cmphi   p0.b, p0/z, z0.b, z0.b
+// CHECK-INST: cmphi p0.b, p0/z, z0.b, z0.b
+// CHECK-ENCODING: [0x10,0x00,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 00 00 24 <unknown>
+
+cmphi   p0.h, p0/z, z0.h, z0.h
+// CHECK-INST: cmphi p0.h, p0/z, z0.h, z0.h
+// CHECK-ENCODING: [0x10,0x00,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 00 40 24 <unknown>
+
+cmphi   p0.s, p0/z, z0.s, z0.s
+// CHECK-INST: cmphi p0.s, p0/z, z0.s, z0.s
+// CHECK-ENCODING: [0x10,0x00,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 00 80 24 <unknown>
+
+cmphi   p0.d, p0/z, z0.d, z0.d
+// CHECK-INST: cmphi p0.d, p0/z, z0.d, z0.d
+// CHECK-ENCODING: [0x10,0x00,0xc0,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 00 c0 24 <unknown>
+
+cmphi   p0.b, p0/z, z0.b, z0.d
+// CHECK-INST: cmphi p0.b, p0/z, z0.b, z0.d
+// CHECK-ENCODING: [0x10,0xc0,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 c0 00 24 <unknown>
+
+cmphi   p0.h, p0/z, z0.h, z0.d
+// CHECK-INST: cmphi p0.h, p0/z, z0.h, z0.d
+// CHECK-ENCODING: [0x10,0xc0,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 c0 40 24 <unknown>
+
+cmphi   p0.s, p0/z, z0.s, z0.d
+// CHECK-INST: cmphi p0.s, p0/z, z0.s, z0.d
+// CHECK-ENCODING: [0x10,0xc0,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 c0 80 24 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/cmphs-diagnostics.s b/llvm/test/MC/AArch64/SVE/cmphs-diagnostics.s
new file mode 100644
index 00000000000..49d23ab56c4
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmphs-diagnostics.s
@@ -0,0 +1,63 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Restricted predicate out of range.
+
+cmphs p0.b, p8/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: cmphs p0.b, p8/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate operation
+
+cmphs p0.b, p0/m, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: cmphs p0.b, p0/m, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid source registers
+
+cmphs p0.b, p0/z, z0.b, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmphs p0.b, p0/z, z0.b, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmphs p0.h, p0/z, z0.h, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmphs p0.h, p0/z, z0.h, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmphs p0.s, p0/z, z0.s, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmphs p0.s, p0/z, z0.s, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmphs p0.d, p0/z, z0.d, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmphs p0.d, p0/z, z0.d, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmphs p0.b, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmphs p0.b, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmphs p0.h, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmphs p0.h, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmphs p0.s, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmphs p0.s, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmphs p0.d, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmphs p0.d, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
diff --git a/llvm/test/MC/AArch64/SVE/cmphs.s b/llvm/test/MC/AArch64/SVE/cmphs.s
new file mode 100644
index 00000000000..79d4913d4a9
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmphs.s
@@ -0,0 +1,51 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+cmphs   p0.b, p0/z, z0.b, z0.b
+// CHECK-INST: cmphs p0.b, p0/z, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0x00,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 00 24 <unknown>
+
+cmphs   p0.h, p0/z, z0.h, z0.h
+// CHECK-INST: cmphs p0.h, p0/z, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x00,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 40 24 <unknown>
+
+cmphs   p0.s, p0/z, z0.s, z0.s
+// CHECK-INST: cmphs p0.s, p0/z, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0x00,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 80 24 <unknown>
+
+cmphs   p0.d, p0/z, z0.d, z0.d
+// CHECK-INST: cmphs p0.d, p0/z, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x00,0xc0,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 00 c0 24 <unknown>
+
+cmphs   p0.b, p0/z, z0.b, z0.d
+// CHECK-INST: cmphs p0.b, p0/z, z0.b, z0.d
+// CHECK-ENCODING: [0x00,0xc0,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 00 24 <unknown>
+
+cmphs   p0.h, p0/z, z0.h, z0.d
+// CHECK-INST: cmphs p0.h, p0/z, z0.h, z0.d
+// CHECK-ENCODING: [0x00,0xc0,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 40 24 <unknown>
+
+cmphs   p0.s, p0/z, z0.s, z0.d
+// CHECK-INST: cmphs p0.s, p0/z, z0.s, z0.d
+// CHECK-ENCODING: [0x00,0xc0,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 80 24 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/cmple-diagnostics.s b/llvm/test/MC/AArch64/SVE/cmple-diagnostics.s
new file mode 100644
index 00000000000..bd871f3c516
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmple-diagnostics.s
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Restricted predicate out of range.
+
+cmple p0.b, p8/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: cmple p0.b, p8/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate operation
+
+cmple p0.b, p0/m, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: cmple p0.b, p0/m, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid source registers
+
+cmple p0.b, p0/z, z0.b, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmple p0.b, p0/z, z0.b, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmple p0.h, p0/z, z0.h, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmple p0.h, p0/z, z0.h, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmple p0.s, p0/z, z0.s, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmple p0.s, p0/z, z0.s, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmple p0.d, p0/z, z0.d, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmple p0.d, p0/z, z0.d, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmple p0.b, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmple p0.b, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmple p0.h, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmple p0.h, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmple p0.s, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmple p0.s, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmple p0.d, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmple p0.d, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/cmple.s b/llvm/test/MC/AArch64/SVE/cmple.s
new file mode 100644
index 00000000000..a684a7e18e1
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmple.s
@@ -0,0 +1,50 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+cmple   p0.b, p0/z, z0.b, z1.b
+// CHECK-INST: cmpge	p0.b, p0/z, z1.b, z0.b
+// CHECK-ENCODING: [0x20,0x80,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 80 00 24 <unknown>
+
+cmple   p0.h, p0/z, z0.h, z1.h
+// CHECK-INST: cmpge	p0.h, p0/z, z1.h, z0.h
+// CHECK-ENCODING: [0x20,0x80,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 80 40 24 <unknown>
+
+cmple   p0.s, p0/z, z0.s, z1.s
+// CHECK-INST: cmpge	p0.s, p0/z, z1.s, z0.s
+// CHECK-ENCODING: [0x20,0x80,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 80 80 24 <unknown>
+
+cmple   p0.d, p0/z, z0.d, z1.d
+// CHECK-INST: cmpge	p0.d, p0/z, z1.d, z0.d
+// CHECK-ENCODING: [0x20,0x80,0xc0,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 80 c0 24 <unknown>
+
+cmple   p0.b, p0/z, z0.b, z0.d
+// CHECK-INST: cmple p0.b, p0/z, z0.b, z0.d
+// CHECK-ENCODING: [0x10,0x60,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 60 00 24 <unknown>
+
+cmple   p0.h, p0/z, z0.h, z0.d
+// CHECK-INST: cmple p0.h, p0/z, z0.h, z0.d
+// CHECK-ENCODING: [0x10,0x60,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 60 40 24 <unknown>
+
+cmple   p0.s, p0/z, z0.s, z0.d
+// CHECK-INST: cmple p0.s, p0/z, z0.s, z0.d
+// CHECK-ENCODING: [0x10,0x60,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 60 80 24 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/cmplo-diagnostics.s b/llvm/test/MC/AArch64/SVE/cmplo-diagnostics.s
new file mode 100644
index 00000000000..55eb036b3ec
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmplo-diagnostics.s
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Restricted predicate out of range.
+
+cmplo p0.b, p8/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: cmplo p0.b, p8/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate operation
+
+cmplo p0.b, p0/m, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: cmplo p0.b, p0/m, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid source registers
+
+cmplo p0.b, p0/z, z0.b, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmplo p0.b, p0/z, z0.b, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmplo p0.h, p0/z, z0.h, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmplo p0.h, p0/z, z0.h, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmplo p0.s, p0/z, z0.s, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmplo p0.s, p0/z, z0.s, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmplo p0.d, p0/z, z0.d, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmplo p0.d, p0/z, z0.d, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmplo p0.b, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmplo p0.b, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmplo p0.h, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmplo p0.h, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmplo p0.s, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmplo p0.s, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmplo p0.d, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmplo p0.d, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/cmplo.s b/llvm/test/MC/AArch64/SVE/cmplo.s
new file mode 100644
index 00000000000..434f7d6e2fd
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmplo.s
@@ -0,0 +1,50 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+cmplo   p0.b, p0/z, z0.b, z1.b
+// CHECK-INST: cmphi	p0.b, p0/z, z1.b, z0.b
+// CHECK-ENCODING: [0x30,0x00,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 00 00 24 <unknown>
+
+cmplo   p0.h, p0/z, z0.h, z1.h
+// CHECK-INST: cmphi	p0.h, p0/z, z1.h, z0.h
+// CHECK-ENCODING: [0x30,0x00,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 00 40 24 <unknown>
+
+cmplo   p0.s, p0/z, z0.s, z1.s
+// CHECK-INST: cmphi	p0.s, p0/z, z1.s, z0.s
+// CHECK-ENCODING: [0x30,0x00,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 00 80 24 <unknown>
+
+cmplo   p0.d, p0/z, z0.d, z1.d
+// CHECK-INST: cmphi	p0.d, p0/z, z1.d, z0.d
+// CHECK-ENCODING: [0x30,0x00,0xc0,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 00 c0 24 <unknown>
+
+cmplo   p0.b, p0/z, z0.b, z0.d
+// CHECK-INST: cmplo p0.b, p0/z, z0.b, z0.d
+// CHECK-ENCODING: [0x00,0xe0,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 00 24 <unknown>
+
+cmplo   p0.h, p0/z, z0.h, z0.d
+// CHECK-INST: cmplo p0.h, p0/z, z0.h, z0.d
+// CHECK-ENCODING: [0x00,0xe0,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 40 24 <unknown>
+
+cmplo   p0.s, p0/z, z0.s, z0.d
+// CHECK-INST: cmplo p0.s, p0/z, z0.s, z0.d
+// CHECK-ENCODING: [0x00,0xe0,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 80 24 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/cmpls-diagnostics.s b/llvm/test/MC/AArch64/SVE/cmpls-diagnostics.s
new file mode 100644
index 00000000000..726cd62963c
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmpls-diagnostics.s
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Restricted predicate out of range.
+
+cmpls p0.b, p8/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: cmpls p0.b, p8/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate operation
+
+cmpls p0.b, p0/m, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: cmpls p0.b, p0/m, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid source registers
+
+cmpls p0.b, p0/z, z0.b, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpls p0.b, p0/z, z0.b, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpls p0.h, p0/z, z0.h, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpls p0.h, p0/z, z0.h, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpls p0.s, p0/z, z0.s, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpls p0.s, p0/z, z0.s, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpls p0.d, p0/z, z0.d, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpls p0.d, p0/z, z0.d, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpls p0.b, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpls p0.b, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpls p0.h, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpls p0.h, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpls p0.s, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpls p0.s, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpls p0.d, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpls p0.d, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/cmpls.s b/llvm/test/MC/AArch64/SVE/cmpls.s
new file mode 100644
index 00000000000..5ba2cf7195d
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmpls.s
@@ -0,0 +1,50 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+cmpls   p0.b, p0/z, z0.b, z1.b
+// CHECK-INST: cmphs	p0.b, p0/z, z1.b, z0.b
+// CHECK-ENCODING: [0x20,0x00,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 00 00 24 <unknown>
+
+cmpls   p0.h, p0/z, z0.h, z1.h
+// CHECK-INST: cmphs	p0.h, p0/z, z1.h, z0.h
+// CHECK-ENCODING: [0x20,0x00,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 00 40 24 <unknown>
+
+cmpls   p0.s, p0/z, z0.s, z1.s
+// CHECK-INST: cmphs	p0.s, p0/z, z1.s, z0.s
+// CHECK-ENCODING: [0x20,0x00,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 00 80 24 <unknown>
+
+cmpls   p0.d, p0/z, z0.d, z1.d
+// CHECK-INST: cmphs	p0.d, p0/z, z1.d, z0.d
+// CHECK-ENCODING: [0x20,0x00,0xc0,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 00 c0 24 <unknown>
+
+cmpls   p0.b, p0/z, z0.b, z0.d
+// CHECK-INST: cmpls p0.b, p0/z, z0.b, z0.d
+// CHECK-ENCODING: [0x10,0xe0,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 e0 00 24 <unknown>
+
+cmpls   p0.h, p0/z, z0.h, z0.d
+// CHECK-INST: cmpls p0.h, p0/z, z0.h, z0.d
+// CHECK-ENCODING: [0x10,0xe0,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 e0 40 24 <unknown>
+
+cmpls   p0.s, p0/z, z0.s, z0.d
+// CHECK-INST: cmpls p0.s, p0/z, z0.s, z0.d
+// CHECK-ENCODING: [0x10,0xe0,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 e0 80 24 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/cmplt-diagnostics.s b/llvm/test/MC/AArch64/SVE/cmplt-diagnostics.s
new file mode 100644
index 00000000000..9ae99414ffb
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmplt-diagnostics.s
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Restricted predicate out of range.
+
+cmplt p0.b, p8/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: cmplt p0.b, p8/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate operation
+
+cmplt p0.b, p0/m, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: cmplt p0.b, p0/m, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid source registers
+
+cmplt p0.b, p0/z, z0.b, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmplt p0.b, p0/z, z0.b, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmplt p0.h, p0/z, z0.h, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmplt p0.h, p0/z, z0.h, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmplt p0.s, p0/z, z0.s, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmplt p0.s, p0/z, z0.s, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmplt p0.d, p0/z, z0.d, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmplt p0.d, p0/z, z0.d, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmplt p0.b, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmplt p0.b, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmplt p0.h, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmplt p0.h, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmplt p0.s, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmplt p0.s, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmplt p0.d, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmplt p0.d, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/cmplt.s b/llvm/test/MC/AArch64/SVE/cmplt.s
new file mode 100644
index 00000000000..86f3d0a80e5
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmplt.s
@@ -0,0 +1,50 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+cmplt   p0.b, p0/z, z0.b, z1.b
+// CHECK-INST: cmpgt	p0.b, p0/z, z1.b, z0.b
+// CHECK-ENCODING: [0x30,0x80,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 80 00 24 <unknown>
+
+cmplt   p0.h, p0/z, z0.h, z1.h
+// CHECK-INST: cmpgt	p0.h, p0/z, z1.h, z0.h
+// CHECK-ENCODING: [0x30,0x80,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 80 40 24 <unknown>
+
+cmplt   p0.s, p0/z, z0.s, z1.s
+// CHECK-INST: cmpgt	p0.s, p0/z, z1.s, z0.s
+// CHECK-ENCODING: [0x30,0x80,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 80 80 24 <unknown>
+
+cmplt   p0.d, p0/z, z0.d, z1.d
+// CHECK-INST: cmpgt	p0.d, p0/z, z1.d, z0.d
+// CHECK-ENCODING: [0x30,0x80,0xc0,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 80 c0 24 <unknown>
+
+cmplt   p0.b, p0/z, z0.b, z0.d
+// CHECK-INST: cmplt p0.b, p0/z, z0.b, z0.d
+// CHECK-ENCODING: [0x00,0x60,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 00 24 <unknown>
+
+cmplt   p0.h, p0/z, z0.h, z0.d
+// CHECK-INST: cmplt p0.h, p0/z, z0.h, z0.d
+// CHECK-ENCODING: [0x00,0x60,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 40 24 <unknown>
+
+cmplt   p0.s, p0/z, z0.s, z0.d
+// CHECK-INST: cmplt p0.s, p0/z, z0.s, z0.d
+// CHECK-ENCODING: [0x00,0x60,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 60 80 24 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/cmpne-diagnostics.s b/llvm/test/MC/AArch64/SVE/cmpne-diagnostics.s
new file mode 100644
index 00000000000..805a319bdb5
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmpne-diagnostics.s
@@ -0,0 +1,62 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Restricted predicate out of range.
+
+cmpne p0.b, p8/z, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: cmpne p0.b, p8/z, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid predicate operation
+
+cmpne p0.b, p0/m, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: cmpne p0.b, p0/m, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid source registers
+
+cmpne p0.b, p0/z, z0.b, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpne p0.b, p0/z, z0.b, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpne p0.h, p0/z, z0.h, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpne p0.h, p0/z, z0.h, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpne p0.s, p0/z, z0.s, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpne p0.s, p0/z, z0.s, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpne p0.d, p0/z, z0.d, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpne p0.d, p0/z, z0.d, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpne p0.b, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpne p0.b, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpne p0.h, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpne p0.h, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpne p0.s, p0/z, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpne p0.s, p0/z, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cmpne p0.d, p0/z, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cmpne p0.d, p0/z, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/cmpne.s b/llvm/test/MC/AArch64/SVE/cmpne.s
new file mode 100644
index 00000000000..ef1557cf0cd
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cmpne.s
@@ -0,0 +1,51 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+cmpne   p0.b, p0/z, z0.b, z0.b
+// CHECK-INST: cmpne p0.b, p0/z, z0.b, z0.b
+// CHECK-ENCODING: [0x10,0xa0,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 a0 00 24 <unknown>
+
+cmpne   p0.h, p0/z, z0.h, z0.h
+// CHECK-INST: cmpne p0.h, p0/z, z0.h, z0.h
+// CHECK-ENCODING: [0x10,0xa0,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 a0 40 24 <unknown>
+
+cmpne   p0.s, p0/z, z0.s, z0.s
+// CHECK-INST: cmpne p0.s, p0/z, z0.s, z0.s
+// CHECK-ENCODING: [0x10,0xa0,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 a0 80 24 <unknown>
+
+cmpne   p0.d, p0/z, z0.d, z0.d
+// CHECK-INST: cmpne p0.d, p0/z, z0.d, z0.d
+// CHECK-ENCODING: [0x10,0xa0,0xc0,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 a0 c0 24 <unknown>
+
+cmpne   p0.b, p0/z, z0.b, z0.d
+// CHECK-INST: cmpne p0.b, p0/z, z0.b, z0.d
+// CHECK-ENCODING: [0x10,0x20,0x00,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 20 00 24 <unknown>
+
+cmpne   p0.h, p0/z, z0.h, z0.d
+// CHECK-INST: cmpne p0.h, p0/z, z0.h, z0.d
+// CHECK-ENCODING: [0x10,0x20,0x40,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 20 40 24 <unknown>
+
+cmpne   p0.s, p0/z, z0.s, z0.d
+// CHECK-INST: cmpne p0.s, p0/z, z0.s, z0.d
+// CHECK-ENCODING: [0x10,0x20,0x80,0x24]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 10 20 80 24 <unknown>