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| author | Alex Bradbury <asb@lowrisc.org> | 2018-10-03 11:14:26 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2018-10-03 11:14:26 +0000 |
| commit | d464ed8c2e4071fc79f213038e570b6319110a7d (patch) | |
| tree | 042506f61eea1f885b1d1d9ab28aa129b5c2a937 | |
| parent | a9ac5994b1ec3b17639c755117c5c56fd40e3e8a (diff) | |
| download | bcm5719-llvm-d464ed8c2e4071fc79f213038e570b6319110a7d.tar.gz bcm5719-llvm-d464ed8c2e4071fc79f213038e570b6319110a7d.zip | |
[RISCV] Remove XLenVT==i32 assumptions from RISCVInstrInfo td
1. brcond operates on an condition.
2. atomic_fence and the pseudo AMO instructions should all take xlen immediates
This allows the same definitions and patterns to work for RV64 (XLenVT==i64).
llvm-svn: 343678
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfo.td | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 10 |
2 files changed, 11 insertions, 11 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 24665bd4acc..e9244ac64c3 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -686,7 +686,7 @@ def Select_GPR_Using_CC_GPR : SelectCC_rrirr<GPR, GPR>; // Match `(brcond (CondOp ..), ..)` and lower to the appropriate RISC-V branch // instruction. class BccPat<PatFrag CondOp, RVInstB Inst> - : Pat<(brcond (i32 (CondOp GPR:$rs1, GPR:$rs2)), bb:$imm12), + : Pat<(brcond (XLenVT (CondOp GPR:$rs1, GPR:$rs2)), bb:$imm12), (Inst GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12)>; def : BccPat<seteq, BEQ>; @@ -697,7 +697,7 @@ def : BccPat<setult, BLTU>; def : BccPat<setuge, BGEU>; class BccSwapPat<PatFrag CondOp, RVInst InstBcc> - : Pat<(brcond (i32 (CondOp GPR:$rs1, GPR:$rs2)), bb:$imm12), + : Pat<(brcond (XLenVT (CondOp GPR:$rs1, GPR:$rs2)), bb:$imm12), (InstBcc GPR:$rs2, GPR:$rs1, bb:$imm12)>; // Condition codes that don't have matching RISC-V branch instructions, but @@ -817,13 +817,13 @@ defm : StPat<store, SW, GPR>, Requires<[IsRV32]>; // Manual: Volume I. // fence acquire -> fence r, rw -def : Pat<(atomic_fence (i32 4), (imm)), (FENCE 0b10, 0b11)>; +def : Pat<(atomic_fence (XLenVT 4), (imm)), (FENCE 0b10, 0b11)>; // fence release -> fence rw, w -def : Pat<(atomic_fence (i32 5), (imm)), (FENCE 0b11, 0b1)>; +def : Pat<(atomic_fence (XLenVT 5), (imm)), (FENCE 0b11, 0b1)>; // fence acq_rel -> fence.tso -def : Pat<(atomic_fence (i32 6), (imm)), (FENCE_TSO)>; +def : Pat<(atomic_fence (XLenVT 6), (imm)), (FENCE_TSO)>; // fence seq_cst -> fence rw, rw -def : Pat<(atomic_fence (i32 7), (imm)), (FENCE 0b11, 0b11)>; +def : Pat<(atomic_fence (XLenVT 7), (imm)), (FENCE 0b11, 0b11)>; // Lowering for atomic load and store is defined in RISCVInstrInfoA.td. // Although these are lowered to fence+load/store instructions defined in the diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td index bf8c835918a..180434e9ff1 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td @@ -145,7 +145,7 @@ def : Pat<(atomic_load_sub_32_seq_cst GPR:$addr, GPR:$incr), /// Pseudo AMOs class PseudoAMO : Pseudo<(outs GPR:$res, GPR:$scratch), - (ins GPR:$addr, GPR:$incr, i32imm:$ordering), []> { + (ins GPR:$addr, GPR:$incr, ixlenimm:$ordering), []> { let Constraints = "@earlyclobber $res,@earlyclobber $scratch"; let mayLoad = 1; let mayStore = 1; @@ -168,7 +168,7 @@ def : Pat<(atomic_load_nand_32_seq_cst GPR:$addr, GPR:$incr), class PseudoMaskedAMO : Pseudo<(outs GPR:$res, GPR:$scratch), - (ins GPR:$addr, GPR:$incr, GPR:$mask, i32imm:$ordering), []> { + (ins GPR:$addr, GPR:$incr, GPR:$mask, ixlenimm:$ordering), []> { let Constraints = "@earlyclobber $res,@earlyclobber $scratch"; let mayLoad = 1; let mayStore = 1; @@ -177,8 +177,8 @@ class PseudoMaskedAMO class PseudoMaskedAMOMinMax : Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2), - (ins GPR:$addr, GPR:$incr, GPR:$mask, i32imm:$sextshamt, - i32imm:$ordering), []> { + (ins GPR:$addr, GPR:$incr, GPR:$mask, ixlenimm:$sextshamt, + ixlenimm:$ordering), []> { let Constraints = "@earlyclobber $res,@earlyclobber $scratch1," "@earlyclobber $scratch2"; let mayLoad = 1; @@ -188,7 +188,7 @@ class PseudoMaskedAMOMinMax class PseudoMaskedAMOUMinUMax : Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2), - (ins GPR:$addr, GPR:$incr, GPR:$mask, i32imm:$ordering), []> { + (ins GPR:$addr, GPR:$incr, GPR:$mask, ixlenimm:$ordering), []> { let Constraints = "@earlyclobber $res,@earlyclobber $scratch1," "@earlyclobber $scratch2"; let mayLoad = 1; |

