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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-06-24 17:42:16 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-06-24 17:42:16 +0000 |
| commit | d40b970616b20d40a8fdfd03c48bb395cae8bc55 (patch) | |
| tree | b22d4fc320e32d9ff40d792a584cde35c75b4960 | |
| parent | bcc6004a0e16ce969b9d9365613b8155806d7933 (diff) | |
| download | bcm5719-llvm-d40b970616b20d40a8fdfd03c48bb395cae8bc55.tar.gz bcm5719-llvm-d40b970616b20d40a8fdfd03c48bb395cae8bc55.zip | |
R600: Remove DIV_INF
This corresponded to an amdil instruction which there is
a 2 instruction equivalent for.
llvm-svn: 211616
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUISelLowering.h | 1 |
2 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp index ca8d0a1626b..6b70d4c010d 100644 --- a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp @@ -1246,7 +1246,8 @@ SDValue AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const { SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib); // float fq = native_divide(fa, fb); - SDValue fq = DAG.getNode(AMDGPUISD::DIV_INF, DL, FLTTY, fa, fb); + SDValue fq = DAG.getNode(ISD::FMUL, DL, FLTTY, + fa, DAG.getNode(AMDGPUISD::RCP, DL, FLTTY, fb)); // fq = trunc(fq); fq = DAG.getNode(ISD::FTRUNC, DL, FLTTY, fq); @@ -2031,7 +2032,6 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const { // AMDIL DAG nodes NODE_NAME_CASE(CALL); NODE_NAME_CASE(UMUL); - NODE_NAME_CASE(DIV_INF); NODE_NAME_CASE(RET_FLAG); NODE_NAME_CASE(BRANCH_COND); diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.h b/llvm/lib/Target/R600/AMDGPUISelLowering.h index 874aa978b53..7d9dcc9ad24 100644 --- a/llvm/lib/Target/R600/AMDGPUISelLowering.h +++ b/llvm/lib/Target/R600/AMDGPUISelLowering.h @@ -165,7 +165,6 @@ enum { FIRST_NUMBER = ISD::BUILTIN_OP_END, CALL, // Function call based on a single integer UMUL, // 32bit unsigned multiplication - DIV_INF, // Divide with infinity returned on zero divisor RET_FLAG, BRANCH_COND, // End AMDIL ISD Opcodes |
