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| author | Misha Brukman <brukman+llvm@gmail.com> | 2004-09-27 18:22:18 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2004-09-27 18:22:18 +0000 |
| commit | d409d38151b0c21baaaa67213e40e856dd537d90 (patch) | |
| tree | 2d3a901e1e3b95ff9e0de97941f86c33d22fab33 | |
| parent | d7dc1ecd4292cf88488c9514c99b7e71ab63ce3f (diff) | |
| download | bcm5719-llvm-d409d38151b0c21baaaa67213e40e856dd537d90.tar.gz bcm5719-llvm-d409d38151b0c21baaaa67213e40e856dd537d90.zip | |
SparcV8 int regs are not only 32-bits in width, but they are 32-bit aligned!
llvm-svn: 16526
| -rw-r--r-- | llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td b/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td index 728c115f861..b3d202bf26f 100644 --- a/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td +++ b/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td @@ -23,7 +23,7 @@ include "../SparcRegisterInfo.td" // FIXME: the register order should be defined in terms of the preferred // allocation order... // -def IntRegs : RegisterClass<i32, 64, [L0, L1, L2, L3, L4, L5, L6, L7, +def IntRegs : RegisterClass<i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7, I0, I1, I2, I3, I4, I5, G1, G2, G3, G4, G5, G6, G7, O0, O1, O2, O3, O4, O5, O7, |
