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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-17 23:17:13 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-17 23:17:13 +0000 |
| commit | d3fec5edc128765e7eeaa007aa3d7c76095d80c2 (patch) | |
| tree | 35eee1e7ba849365ccb8b36a114030a9493ac279 | |
| parent | d7357a9b8e3d3ffff505ef767081e042b8ef5e24 (diff) | |
| download | bcm5719-llvm-d3fec5edc128765e7eeaa007aa3d7c76095d80c2.tar.gz bcm5719-llvm-d3fec5edc128765e7eeaa007aa3d7c76095d80c2.zip | |
Zap the last reference to allocation_order_begin().
llvm-svn: 133310
| -rw-r--r-- | llvm/lib/Target/TargetRegisterInfo.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/TargetRegisterInfo.cpp b/llvm/lib/Target/TargetRegisterInfo.cpp index e36e1364504..bae3343a850 100644 --- a/llvm/lib/Target/TargetRegisterInfo.cpp +++ b/llvm/lib/Target/TargetRegisterInfo.cpp @@ -79,9 +79,9 @@ TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const { /// registers for the specific register class. static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R){ - for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), - E = RC->allocation_order_end(MF); I != E; ++I) - R.set(*I); + ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF); + for (unsigned i = 0; i != Order.size(); ++i) + R.set(Order[i]); } BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, |
