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| author | Silviu Baranga <silviu.baranga@arm.com> | 2012-04-05 16:13:15 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2012-04-05 16:13:15 +0000 |
| commit | d365397daab47927c20be24dce4ddeac8762bcf8 (patch) | |
| tree | b165ad5cca9263318deccd1e94745b26448f36cc | |
| parent | 7fdf9ef15da7d17b09f89f9c5bcef9314bcb6538 (diff) | |
| download | bcm5719-llvm-d365397daab47927c20be24dce4ddeac8762bcf8.tar.gz bcm5719-llvm-d365397daab47927c20be24dce4ddeac8762bcf8.zip | |
Added support for handling unpredictable arithmetic instructions on ARM.
llvm-svn: 154100
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 2 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt | 12 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt | 7 |
3 files changed, 9 insertions, 12 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 37d53b09a79..eb30f79eff8 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -3244,6 +3244,8 @@ class AAI<bits<8> op27_20, bits<8> op11_4, string opc, let Inst{19-16} = Rn; let Inst{15-12} = Rd; let Inst{3-0} = Rm; + + let Unpredictable{11-8} = 0b1111; } // Saturating add/subtract diff --git a/llvm/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt b/llvm/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt deleted file mode 100644 index 067dcb36a7e..00000000000 --- a/llvm/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt +++ /dev/null @@ -1,12 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} - -# Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 0: 1: 1: 0| 0: 0: 1: 1| 0: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# The bytes have Inst{4} = 1, so it's not an LDRT Encoding A2 instruction. -0x10 0x51 0x37 0xe6 - - diff --git a/llvm/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt b/llvm/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt new file mode 100644 index 00000000000..8ec49cad349 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s + +# CHECK: warning: potentially undefined +# CHECK: shadd16 r5, r7, r0 +0x10 0x51 0x37 0xe6 + + |
