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| author | Evan Cheng <evan.cheng@apple.com> | 2009-11-17 00:55:55 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-11-17 00:55:55 +0000 |
| commit | d33400e636a5da5f3c39d59cd3d3a9042f285572 (patch) | |
| tree | 47787d85addbe267974b6606989e1cef49200f69 | |
| parent | 6c254bf522fe84eae031f3b056dbf281b929efa3 (diff) | |
| download | bcm5719-llvm-d33400e636a5da5f3c39d59cd3d3a9042f285572.tar.gz bcm5719-llvm-d33400e636a5da5f3c39d59cd3d3a9042f285572.zip | |
MOV64rm should be marked isReMaterializable.
llvm-svn: 89019
| -rw-r--r-- | llvm/lib/Target/X86/X86Instr64bit.td | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/2009-11-16-MachineLICM.ll | 42 |
2 files changed, 43 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86Instr64bit.td b/llvm/lib/Target/X86/X86Instr64bit.td index 3edced7b43e..a01534b70d2 100644 --- a/llvm/lib/Target/X86/X86Instr64bit.td +++ b/llvm/lib/Target/X86/X86Instr64bit.td @@ -309,7 +309,7 @@ def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), [(set GR64:$dst, i64immSExt32:$src)]>; } -let canFoldAsLoad = 1 in +let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), "mov{q}\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (load addr:$src))]>; diff --git a/llvm/test/CodeGen/X86/2009-11-16-MachineLICM.ll b/llvm/test/CodeGen/X86/2009-11-16-MachineLICM.ll new file mode 100644 index 00000000000..a7c202076da --- /dev/null +++ b/llvm/test/CodeGen/X86/2009-11-16-MachineLICM.ll @@ -0,0 +1,42 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; rdar://7395200 + +@g = common global [4 x float] zeroinitializer, align 16 ; <[4 x float]*> [#uses=4] + +define void @foo(i32 %n, float* nocapture %x) nounwind ssp { +entry: +; CHECK: foo: + %0 = icmp sgt i32 %n, 0 ; <i1> [#uses=1] + br i1 %0, label %bb.nph, label %return + +bb.nph: ; preds = %entry +; CHECK: movq _g@GOTPCREL(%rip), %rcx + %tmp = zext i32 %n to i64 ; <i64> [#uses=1] + br label %bb + +bb: ; preds = %bb, %bb.nph +; CHECK: LBB1_2: + %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i64> [#uses=2] + %tmp9 = shl i64 %indvar, 2 ; <i64> [#uses=4] + %tmp1016 = or i64 %tmp9, 1 ; <i64> [#uses=1] + %scevgep = getelementptr float* %x, i64 %tmp1016 ; <float*> [#uses=1] + %tmp1117 = or i64 %tmp9, 2 ; <i64> [#uses=1] + %scevgep12 = getelementptr float* %x, i64 %tmp1117 ; <float*> [#uses=1] + %tmp1318 = or i64 %tmp9, 3 ; <i64> [#uses=1] + %scevgep14 = getelementptr float* %x, i64 %tmp1318 ; <float*> [#uses=1] + %x_addr.03 = getelementptr float* %x, i64 %tmp9 ; <float*> [#uses=1] + %1 = load float* getelementptr inbounds ([4 x float]* @g, i64 0, i64 0), align 16 ; <float> [#uses=1] + store float %1, float* %x_addr.03, align 4 + %2 = load float* getelementptr inbounds ([4 x float]* @g, i64 0, i64 1), align 4 ; <float> [#uses=1] + store float %2, float* %scevgep, align 4 + %3 = load float* getelementptr inbounds ([4 x float]* @g, i64 0, i64 2), align 8 ; <float> [#uses=1] + store float %3, float* %scevgep12, align 4 + %4 = load float* getelementptr inbounds ([4 x float]* @g, i64 0, i64 3), align 4 ; <float> [#uses=1] + store float %4, float* %scevgep14, align 4 + %indvar.next = add i64 %indvar, 1 ; <i64> [#uses=2] + %exitcond = icmp eq i64 %indvar.next, %tmp ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb, %entry + ret void +} |

