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| author | Tim Northover <Tim.Northover@arm.com> | 2013-02-14 16:22:14 +0000 |
|---|---|---|
| committer | Tim Northover <Tim.Northover@arm.com> | 2013-02-14 16:22:14 +0000 |
| commit | d21ddb90427959d3b4a63049d89cbcda6ef5f6d4 (patch) | |
| tree | 08013fa685cd46f6618e6a07d70fece4b2303099 | |
| parent | f471c3e63a436b24d30a593d97ab551a68f2622f (diff) | |
| download | bcm5719-llvm-d21ddb90427959d3b4a63049d89cbcda6ef5f6d4.tar.gz bcm5719-llvm-d21ddb90427959d3b4a63049d89cbcda6ef5f6d4.zip | |
AArch64: stop claiming that NEON registers are usable for now.
If vector types have legal register classes, then LLVM bypasses LegalizeTypes
on them, which causes faults currently since the code to handle them isn't in
place.
This fixes test failures when AArch64 is the default target.
llvm-svn: 175172
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index ff28dc17fdf..2c11547c467 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -57,17 +57,6 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM) addRegisterClass(MVT::f64, &AArch64::FPR64RegClass); addRegisterClass(MVT::f128, &AArch64::FPR128RegClass); - // And the vectors - addRegisterClass(MVT::v8i8, &AArch64::VPR64RegClass); - addRegisterClass(MVT::v4i16, &AArch64::VPR64RegClass); - addRegisterClass(MVT::v2i32, &AArch64::VPR64RegClass); - addRegisterClass(MVT::v2f32, &AArch64::VPR64RegClass); - addRegisterClass(MVT::v16i8, &AArch64::VPR128RegClass); - addRegisterClass(MVT::v8i16, &AArch64::VPR128RegClass); - addRegisterClass(MVT::v4i32, &AArch64::VPR128RegClass); - addRegisterClass(MVT::v4f32, &AArch64::VPR128RegClass); - addRegisterClass(MVT::v2f64, &AArch64::VPR128RegClass); - computeRegisterProperties(); // Some atomic operations can be folded into load-acquire or store-release |
