[llvm-mca] Simplify code in class Scheduler. NFCI

llvm-svn: 347985

4 files changed, 18 insertions, 18 deletions

diff --git a/llvm/tools/llvm-mca/include/HardwareUnits/LSUnit.h b/llvm/tools/llvm-mca/include/HardwareUnits/LSUnit.h
index f8c0722b540..3f37651ad8d 100644
--- a/llvm/tools/llvm-mca/include/HardwareUnits/LSUnit.h
+++ b/llvm/tools/llvm-mca/include/HardwareUnits/LSUnit.h
@@ -24,6 +24,7 @@ namespace llvm {
 namespace mca {
 
 class InstRef;
+class Scheduler;
 
 /// A Load/Store Unit implementing a load and store queues.
 ///
@@ -110,7 +111,7 @@ class LSUnit : public HardwareUnit {
   //
   // This class doesn't know about the latency of a load instruction. So, it
   // conservatively/pessimistically assumes that the latency of a load opcode
-  // matches the instruction latency. 
+  // matches the instruction latency.
   //
   // FIXME: In the absence of cache misses (i.e. L1I/L1D/iTLB/dTLB hits/misses),
   // and load/store conflicts, the latency of a load is determined by the depth
@@ -195,7 +196,7 @@ public:
   // becomes available to the users. At that point, the load no longer needs to
   // be tracked by the load queue.
   // FIXME: For simplicity, we optimistically assume a similar behavior for
-  // store instructions.  In practice, store operation don't tend to leave the
+  // store instructions. In practice, store operations don't tend to leave the
   // store queue until they reach the 'Retired' stage (See PR39830).
   void onInstructionExecuted(const InstRef &IR);
 };
diff --git a/llvm/tools/llvm-mca/include/HardwareUnits/Scheduler.h b/llvm/tools/llvm-mca/include/HardwareUnits/Scheduler.h
index 17332b430d2..a8d00d2a60c 100644
--- a/llvm/tools/llvm-mca/include/HardwareUnits/Scheduler.h
+++ b/llvm/tools/llvm-mca/include/HardwareUnits/Scheduler.h
@@ -85,7 +85,7 @@ public:
 /// transition (i.e. from state IS_READY, to state IS_EXECUTING). An Instruction
 /// leaves the IssuedSet when it reaches the write-back stage.
 class Scheduler : public HardwareUnit {
-  LSUnit *LSU;
+  LSUnit &LSU;
 
   // Instruction selection strategy for this Scheduler.
   std::unique_ptr<SchedulerStrategy> Strategy;
@@ -117,16 +117,15 @@ class Scheduler : public HardwareUnit {
   void promoteToReadySet(SmallVectorImpl<InstRef> &Ready);
 
 public:
-  Scheduler(const MCSchedModel &Model, LSUnit *Lsu)
-      : LSU(Lsu), Resources(make_unique<ResourceManager>(Model)) {
-    initializeStrategy(nullptr);
-  }
-  Scheduler(const MCSchedModel &Model, LSUnit *Lsu,
+  Scheduler(const MCSchedModel &Model, LSUnit &Lsu)
+      : Scheduler(Model, Lsu, nullptr) {}
+
+  Scheduler(const MCSchedModel &Model, LSUnit &Lsu,
             std::unique_ptr<SchedulerStrategy> SelectStrategy)
-      : LSU(Lsu), Resources(make_unique<ResourceManager>(Model)) {
-    initializeStrategy(std::move(SelectStrategy));
-  }
-  Scheduler(std::unique_ptr<ResourceManager> RM, LSUnit *Lsu,
+      : Scheduler(make_unique<ResourceManager>(Model), Lsu,
+                  std::move(SelectStrategy)) {}
+
+  Scheduler(std::unique_ptr<ResourceManager> RM, LSUnit &Lsu,
             std::unique_ptr<SchedulerStrategy> SelectStrategy)
       : LSU(Lsu), Resources(std::move(RM)) {
     initializeStrategy(std::move(SelectStrategy));
diff --git a/llvm/tools/llvm-mca/lib/Context.cpp b/llvm/tools/llvm-mca/lib/Context.cpp
index d472ae3313a..17b992aac9c 100644
--- a/llvm/tools/llvm-mca/lib/Context.cpp
+++ b/llvm/tools/llvm-mca/lib/Context.cpp
@@ -37,7 +37,7 @@ Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
   auto PRF = llvm::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
   auto LSU = llvm::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
                                        Opts.StoreQueueSize, Opts.AssumeNoAlias);
-  auto HWS = llvm::make_unique<Scheduler>(SM, LSU.get());
+  auto HWS = llvm::make_unique<Scheduler>(SM, *LSU);
 
   // Create the pipeline stages.
   auto Fetch = llvm::make_unique<EntryStage>(SrcMgr);
diff --git a/llvm/tools/llvm-mca/lib/HardwareUnits/Scheduler.cpp b/llvm/tools/llvm-mca/lib/HardwareUnits/Scheduler.cpp
index b1ac8d99b86..f0ac59e5bc2 100644
--- a/llvm/tools/llvm-mca/lib/HardwareUnits/Scheduler.cpp
+++ b/llvm/tools/llvm-mca/lib/HardwareUnits/Scheduler.cpp
@@ -51,7 +51,7 @@ Scheduler::Status Scheduler::isAvailable(const InstRef &IR) const {
   }
 
   // Give lower priority to LSUnit stall events.
-  switch (LSU->isAvailable(IR)) {
+  switch (LSU.isAvailable(IR)) {
   case LSUnit::LSU_LQUEUE_FULL:
     return Scheduler::SC_LOAD_QUEUE_FULL;
   case LSUnit::LSU_SQUEUE_FULL:
@@ -80,7 +80,7 @@ void Scheduler::issueInstructionImpl(
   if (IS->isExecuting())
     IssuedSet.emplace_back(IR);
   else if (IS->isExecuted())
-    LSU->onInstructionExecuted(IR);
+    LSU.onInstructionExecuted(IR);
 }
 
 // Release the buffered resources and issue the instruction.
@@ -170,7 +170,7 @@ void Scheduler::updateIssuedSet(SmallVectorImpl<InstRef> &Executed) {
     }
 
     // Instruction IR has completed execution.
-    LSU->onInstructionExecuted(IR);
+    LSU.onInstructionExecuted(IR);
     Executed.emplace_back(IR);
     ++RemovedElements;
     IR.invalidate();
@@ -213,7 +213,7 @@ void Scheduler::dispatch(const InstRef &IR) {
   // If necessary, reserve queue entries in the load-store unit (LSU).
   bool IsMemOp = Desc.MayLoad || Desc.MayStore;
   if (IsMemOp)
-    LSU->dispatch(IR);
+    LSU.dispatch(IR);
 
   if (!isReady(IR)) {
     LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR << " to the WaitSet\n");
@@ -238,7 +238,7 @@ void Scheduler::dispatch(const InstRef &IR) {
 bool Scheduler::isReady(const InstRef &IR) const {
   const InstrDesc &Desc = IR.getInstruction()->getDesc();
   bool IsMemOp = Desc.MayLoad || Desc.MayStore;
-  return IR.getInstruction()->isReady() && (!IsMemOp || LSU->isReady(IR));
+  return IR.getInstruction()->isReady() && (!IsMemOp || LSU.isReady(IR));
 }
 
 } // namespace mca