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| author | Bob Wilson <bob.wilson@apple.com> | 2011-08-13 05:14:55 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2011-08-13 05:14:55 +0000 |
| commit | d1de7764be8af9c2dccd44d404f0fb187c6d47f3 (patch) | |
| tree | 23694343c786d0e736cd4033733d044310aece0d | |
| parent | 445c24f8f032da226d9495cc441c1c2ce39d2155 (diff) | |
| download | bcm5719-llvm-d1de7764be8af9c2dccd44d404f0fb187c6d47f3.tar.gz bcm5719-llvm-d1de7764be8af9c2dccd44d404f0fb187c6d47f3.zip | |
Expand VMOVQQQQ pseudo instructions.
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed. Our register allocator must be awesome!
llvm-svn: 137551
| -rw-r--r-- | llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 46 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll | 13 |
2 files changed, 59 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp index a4fcfd51bfd..a1be94ab878 100644 --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -998,6 +998,52 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, return true; } + case ARM::VMOVQQQQ: { + unsigned DstReg = MI.getOperand(0).getReg(); + bool DstIsDead = MI.getOperand(0).isDead(); + unsigned Dst0 = TRI->getSubReg(DstReg, ARM::qsub_0); + unsigned Dst1 = TRI->getSubReg(DstReg, ARM::qsub_1); + unsigned Dst2 = TRI->getSubReg(DstReg, ARM::qsub_2); + unsigned Dst3 = TRI->getSubReg(DstReg, ARM::qsub_3); + unsigned SrcReg = MI.getOperand(1).getReg(); + bool SrcIsKill = MI.getOperand(1).isKill(); + unsigned Src0 = TRI->getSubReg(SrcReg, ARM::qsub_0); + unsigned Src1 = TRI->getSubReg(SrcReg, ARM::qsub_1); + unsigned Src2 = TRI->getSubReg(SrcReg, ARM::qsub_2); + unsigned Src3 = TRI->getSubReg(SrcReg, ARM::qsub_3); + MachineInstrBuilder Mov0 = + AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(ARM::VORRq)) + .addReg(Dst0, + RegState::Define | getDeadRegState(DstIsDead)) + .addReg(Src0, getKillRegState(SrcIsKill)) + .addReg(Src0, getKillRegState(SrcIsKill))); + MachineInstrBuilder Mov1 = + AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(ARM::VORRq)) + .addReg(Dst1, + RegState::Define | getDeadRegState(DstIsDead)) + .addReg(Src1, getKillRegState(SrcIsKill)) + .addReg(Src1, getKillRegState(SrcIsKill))); + MachineInstrBuilder Mov2 = + AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(ARM::VORRq)) + .addReg(Dst2, + RegState::Define | getDeadRegState(DstIsDead)) + .addReg(Src2, getKillRegState(SrcIsKill)) + .addReg(Src2, getKillRegState(SrcIsKill))); + MachineInstrBuilder Mov3 = + AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(ARM::VORRq)) + .addReg(Dst3, + RegState::Define | getDeadRegState(DstIsDead)) + .addReg(Src3, getKillRegState(SrcIsKill)) + .addReg(Src3, getKillRegState(SrcIsKill))); + TransferImpOps(MI, Mov0, Mov3); + MI.eraseFromParent(); + return true; + } + case ARM::VLDMQIA: { unsigned NewOpc = ARM::VLDMDIA; MachineInstrBuilder MIB = diff --git a/llvm/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll b/llvm/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll new file mode 100644 index 00000000000..6afa0161ca4 --- /dev/null +++ b/llvm/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll @@ -0,0 +1,13 @@ +; RUN: llc %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 -O0 +; The following test is supposed to produce a VMOVQQQQ pseudo instruction. +; Make sure that it gets expanded; otherwise, the compile fails when trying +; to print the pseudo-instruction. + +define void @test_vmovqqqq_pseudo() nounwind ssp { +entry: + %vld3_lane = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> zeroinitializer, i32 7, i32 2) + store { <8 x i16>, <8 x i16>, <8 x i16> } %vld3_lane, { <8 x i16>, <8 x i16>, <8 x i16> }* undef + ret void +} + +declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly |
