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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-11-09 02:38:51 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-11-09 02:38:51 +0000 |
| commit | d1c58ed8a7d51ee476b0b1638fa3a8bb8b0b445a (patch) | |
| tree | 3817690a89d0d0d45eb293d26db3e2b4a5232fbc | |
| parent | 59886d00ec2c1a11a2b86b2ed6581840e2269e9e (diff) | |
| download | bcm5719-llvm-d1c58ed8a7d51ee476b0b1638fa3a8bb8b0b445a.tar.gz bcm5719-llvm-d1c58ed8a7d51ee476b0b1638fa3a8bb8b0b445a.zip | |
[mips] Make sure there is a chain edge dependency between loads that read
formal arguments on the stack and stores created afterwards. We need this to
ensure tail call optimized function calls do not write over the argument area
of the stack before it is read out.
llvm-svn: 194309
| -rw-r--r-- | llvm/lib/Target/Mips/MipsISelLowering.cpp | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/i64arg.ll | 14 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/tailcall.ll | 13 |
3 files changed, 25 insertions, 10 deletions
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 7a0e666ecfe..5f82b4e69c8 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -2650,9 +2650,11 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain, // Create load nodes to retrieve arguments from the stack SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); - InVals.push_back(DAG.getLoad(ValVT, DL, Chain, FIN, - MachinePointerInfo::getFixedStack(FI), - false, false, false, 0)); + SDValue Load = DAG.getLoad(ValVT, DL, Chain, FIN, + MachinePointerInfo::getFixedStack(FI), + false, false, false, 0); + InVals.push_back(Load); + OutChains.push_back(Load.getValue(1)); } } diff --git a/llvm/test/CodeGen/Mips/i64arg.ll b/llvm/test/CodeGen/Mips/i64arg.ll index b038ad5bf74..5b2d1351803 100644 --- a/llvm/test/CodeGen/Mips/i64arg.ll +++ b/llvm/test/CodeGen/Mips/i64arg.ll @@ -2,16 +2,16 @@ define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind { entry: -; CHECK: move $[[R1:[0-9]+]], $5 -; CHECK: move $[[R0:[0-9]+]], $4 -; CHECK: ori $6, ${{[0-9]+}}, 3855 -; CHECK: ori $7, ${{[0-9]+}}, 22136 -; CHECK: lw $25, %call16(ff1) +; CHECK-DAG: lw $[[R2:[0-9]+]], 80($sp) +; CHECK-DAG: lw $[[R3:[0-9]+]], 84($sp) +; CHECK-DAG: move $[[R1:[0-9]+]], $5 +; CHECK-DAG: move $[[R0:[0-9]+]], $4 +; CHECK-DAG: ori $6, ${{[0-9]+}}, 3855 +; CHECK-DAG: ori $7, ${{[0-9]+}}, 22136 +; CHECK-DAG: lw $25, %call16(ff1) ; CHECK: jalr tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind ; CHECK-DAG: lw $25, %call16(ff2) -; CHECK-DAG: lw $[[R2:[0-9]+]], 80($sp) -; CHECK-DAG: lw $[[R3:[0-9]+]], 84($sp) ; CHECK-DAG: move $4, $[[R2]] ; CHECK-DAG: move $5, $[[R3]] ; CHECK: jalr $25 diff --git a/llvm/test/CodeGen/Mips/tailcall.ll b/llvm/test/CodeGen/Mips/tailcall.ll index bcd33fca70e..30f47abc06c 100644 --- a/llvm/test/CodeGen/Mips/tailcall.ll +++ b/llvm/test/CodeGen/Mips/tailcall.ll @@ -243,3 +243,16 @@ entry: ret i32 %call } +; Check that there is a chain edge between the load and store nodes. +; +; PIC32-LABEL: caller14: +; PIC32: lw ${{[0-9]+}}, 16($sp) +; PIC32: sw $4, 16($sp) + +define void @caller14(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) { +entry: + tail call void @callee14(i32 %e, i32 %b, i32 %c, i32 %d, i32 %a) + ret void +} + +declare void @callee14(i32, i32, i32, i32, i32) |
