[X86] Add ADD16i16/ADD32i32/ADD64i32 and similar to the scheduler models to match ADD8i8.

Also move ADC8i8 and SBB8i8 in the Sandy Bridge model to the same class as ADC8ri and SBB8ri. That seems more accurate since its the 8i8 is just the register forced to AL instead of coming from modrm.

llvm-svn: 327820

6 files changed, 80 insertions, 74 deletions

diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index 8efc23342d1..f7b6ade59de 100755
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -599,6 +599,7 @@ def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
   let ResourceCycles = [1];
 }
 def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri")>;
+def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)i")>;
 def: InstRW<[BWWriteResGroup6], (instregex "ADC(8|16|32|64)rr")>;
 def: InstRW<[BWWriteResGroup6], (instregex "ADCX(32|64)rr")>;
 def: InstRW<[BWWriteResGroup6], (instregex "ADOX(32|64)rr")>;
@@ -622,6 +623,7 @@ def: InstRW<[BWWriteResGroup6], (instregex "SAR(8|16|32|64)r1")>;
 def: InstRW<[BWWriteResGroup6], (instregex "SAR(8|16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup6], (instregex "SARX(32|64)rr")>;
 def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)ri")>;
+def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)i")>;
 def: InstRW<[BWWriteResGroup6], (instregex "SBB(8|16|32|64)rr")>;
 def: InstRW<[BWWriteResGroup6], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r")>;
 def: InstRW<[BWWriteResGroup6], (instregex "SHL(8|16|32|64)r1")>;
@@ -853,16 +855,16 @@ def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
 }
 def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)rr")>;
-def: InstRW<[BWWriteResGroup9], (instregex "ADD8i8")>;
+def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)i")>;
 def: InstRW<[BWWriteResGroup9], (instregex "AND(8|16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "AND(8|16|32|64)rr")>;
-def: InstRW<[BWWriteResGroup9], (instregex "AND8i8")>;
+def: InstRW<[BWWriteResGroup9], (instregex "AND(8|16|32|64)i")>;
 def: InstRW<[BWWriteResGroup9], (instregex "CBW")>;
 def: InstRW<[BWWriteResGroup9], (instregex "CLC")>;
 def: InstRW<[BWWriteResGroup9], (instregex "CMC")>;
 def: InstRW<[BWWriteResGroup9], (instregex "CMP(8|16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "CMP(8|16|32|64)rr")>;
-def: InstRW<[BWWriteResGroup9], (instregex "CMP8i8")>;
+def: InstRW<[BWWriteResGroup9], (instregex "CMP(8|16|32|64)i")>;
 def: InstRW<[BWWriteResGroup9], (instrs CWDE)>;
 def: InstRW<[BWWriteResGroup9], (instregex "DEC(8|16|32|64)r")>;
 def: InstRW<[BWWriteResGroup9], (instregex "INC(8|16|32|64)r")>;
@@ -879,7 +881,7 @@ def: InstRW<[BWWriteResGroup9], (instregex "NOOP")>;
 def: InstRW<[BWWriteResGroup9], (instregex "NOT(8|16|32|64)r")>;
 def: InstRW<[BWWriteResGroup9], (instregex "OR(8|16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "OR(8|16|32|64)rr")>;
-def: InstRW<[BWWriteResGroup9], (instregex "OR8i8")>;
+def: InstRW<[BWWriteResGroup9], (instregex "OR(8|16|32|64)i")>;
 def: InstRW<[BWWriteResGroup9], (instregex "SAHF")>;
 def: InstRW<[BWWriteResGroup9], (instregex "SGDT64m")>;
 def: InstRW<[BWWriteResGroup9], (instregex "SIDT64m")>;
@@ -889,7 +891,7 @@ def: InstRW<[BWWriteResGroup9], (instregex "STC")>;
 def: InstRW<[BWWriteResGroup9], (instregex "STRm")>;
 def: InstRW<[BWWriteResGroup9], (instregex "SUB(8|16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "SUB(8|16|32|64)rr")>;
-def: InstRW<[BWWriteResGroup9], (instregex "SUB8i8")>;
+def: InstRW<[BWWriteResGroup9], (instregex "SUB(8|16|32|64)i")>;
 def: InstRW<[BWWriteResGroup9], (instregex "SYSCALL")>;
 def: InstRW<[BWWriteResGroup9], (instregex "TEST(8|16|32|64)rr")>;
 def: InstRW<[BWWriteResGroup9], (instregex "TEST8i8")>;
@@ -897,7 +899,7 @@ def: InstRW<[BWWriteResGroup9], (instregex "TEST8ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "XCHG(16|32|64)rr")>;
 def: InstRW<[BWWriteResGroup9], (instregex "XOR(8|16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "XOR(8|16|32|64)rr")>;
-def: InstRW<[BWWriteResGroup9], (instregex "XOR8i8")>;
+def: InstRW<[BWWriteResGroup9], (instregex "XOR(8|16|32|64)i")>;
 
 def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
   let Latency = 1;
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index 7426a0d03e9..8a60c7b8b6b 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -1270,16 +1270,16 @@ def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
 }
 def: InstRW<[HWWriteResGroup10], (instregex "ADD(8|16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "ADD(8|16|32|64)rr")>;
-def: InstRW<[HWWriteResGroup10], (instregex "ADD8i8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "ADD(8|16|32|64)i")>;
 def: InstRW<[HWWriteResGroup10], (instregex "AND(8|16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "AND(8|16|32|64)rr")>;
-def: InstRW<[HWWriteResGroup10], (instregex "AND8i8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "AND(8|16|32|64)i")>;
 def: InstRW<[HWWriteResGroup10], (instregex "CBW")>;
 def: InstRW<[HWWriteResGroup10], (instregex "CLC")>;
 def: InstRW<[HWWriteResGroup10], (instregex "CMC")>;
 def: InstRW<[HWWriteResGroup10], (instregex "CMP(8|16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "CMP(8|16|32|64)rr")>;
-def: InstRW<[HWWriteResGroup10], (instregex "CMP8i8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "CMP(8|16|32|64)i")>;
 def: InstRW<[HWWriteResGroup10], (instrs CWDE)>;
 def: InstRW<[HWWriteResGroup10], (instregex "DEC(8|16|32|64)r")>;
 def: InstRW<[HWWriteResGroup10], (instregex "INC(8|16|32|64)r")>;
@@ -1296,7 +1296,7 @@ def: InstRW<[HWWriteResGroup10], (instregex "NOOP")>;
 def: InstRW<[HWWriteResGroup10], (instregex "NOT(8|16|32|64)r")>;
 def: InstRW<[HWWriteResGroup10], (instregex "OR(8|16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "OR(8|16|32|64)rr")>;
-def: InstRW<[HWWriteResGroup10], (instregex "OR8i8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "OR(8|16|32|64)i")>;
 def: InstRW<[HWWriteResGroup10], (instregex "SAHF")>;
 def: InstRW<[HWWriteResGroup10], (instregex "SGDT64m")>;
 def: InstRW<[HWWriteResGroup10], (instregex "SIDT64m")>;
@@ -1306,7 +1306,7 @@ def: InstRW<[HWWriteResGroup10], (instregex "STC")>;
 def: InstRW<[HWWriteResGroup10], (instregex "STRm")>;
 def: InstRW<[HWWriteResGroup10], (instregex "SUB(8|16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "SUB(8|16|32|64)rr")>;
-def: InstRW<[HWWriteResGroup10], (instregex "SUB8i8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "SUB(8|16|32|64)i")>;
 def: InstRW<[HWWriteResGroup10], (instregex "SYSCALL")>;
 def: InstRW<[HWWriteResGroup10], (instregex "TEST(8|16|32|64)rr")>;
 def: InstRW<[HWWriteResGroup10], (instregex "TEST8i8")>;
@@ -1314,7 +1314,7 @@ def: InstRW<[HWWriteResGroup10], (instregex "TEST8ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
 def: InstRW<[HWWriteResGroup10], (instregex "XOR(8|16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "XOR(8|16|32|64)rr")>;
-def: InstRW<[HWWriteResGroup10], (instregex "XOR8i8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "XOR(8|16|32|64)i")>;
 
 def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> {
   let Latency = 6;
@@ -2086,13 +2086,13 @@ def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {
 }
 def: InstRW<[HWWriteResGroup35], (instregex "ADC(8|16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup35], (instregex "ADC(8|16|32|64)rr")>;
-def: InstRW<[HWWriteResGroup35], (instregex "ADC8i8")>;
+def: InstRW<[HWWriteResGroup35], (instregex "ADC(8|16|32|64)i")>;
 def: InstRW<[HWWriteResGroup35], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr")>;
 def: InstRW<[HWWriteResGroup35], (instrs CWD)>;
 def: InstRW<[HWWriteResGroup35], (instregex "JRCXZ")>;
 def: InstRW<[HWWriteResGroup35], (instregex "SBB(8|16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup35], (instregex "SBB(8|16|32|64)rr")>;
-def: InstRW<[HWWriteResGroup35], (instregex "SBB8i8")>;
+def: InstRW<[HWWriteResGroup35], (instregex "SBB(8|16|32|64)i")>;
 def: InstRW<[HWWriteResGroup35], (instregex "SET(A|BE)r")>;
 
 def HWWriteResGroup36 : SchedWriteRes<[HWPort5,HWPort23]> {
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td
index fac1c48553a..f934e4abfeb 100644
--- a/llvm/lib/Target/X86/X86SchedSandyBridge.td
+++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td
@@ -654,15 +654,15 @@ def SBWriteResGroup6 : SchedWriteRes<[SBPort015]> {
 }
 def: InstRW<[SBWriteResGroup6], (instregex "ADD(8|16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup6], (instregex "ADD(8|16|32|64)rr")>;
-def: InstRW<[SBWriteResGroup6], (instregex "ADD8i8")>;
+def: InstRW<[SBWriteResGroup6], (instregex "ADD(8|16|32|64)i")>;
 def: InstRW<[SBWriteResGroup6], (instregex "AND(8|16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup6], (instregex "AND(8|16|32|64)rr")>;
-def: InstRW<[SBWriteResGroup6], (instregex "AND8i8")>;
+def: InstRW<[SBWriteResGroup6], (instregex "AND(8|16|32|64)i")>;
 def: InstRW<[SBWriteResGroup6], (instregex "CBW")>;
 def: InstRW<[SBWriteResGroup6], (instregex "CMC")>;
 def: InstRW<[SBWriteResGroup6], (instregex "CMP(8|16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup6], (instregex "CMP(8|16|32|64)rr")>;
-def: InstRW<[SBWriteResGroup6], (instregex "CMP8i8")>;
+def: InstRW<[SBWriteResGroup6], (instregex "CMP(8|16|32|64)i")>;
 def: InstRW<[SBWriteResGroup6], (instrs CWDE)>;
 def: InstRW<[SBWriteResGroup6], (instregex "DEC(8|16|32|64)r")>;
 def: InstRW<[SBWriteResGroup6], (instregex "INC(8|16|32|64)r")>;
@@ -682,7 +682,7 @@ def: InstRW<[SBWriteResGroup6], (instregex "NEG(8|16|32|64)r")>;
 def: InstRW<[SBWriteResGroup6], (instregex "NOT(8|16|32|64)r")>;
 def: InstRW<[SBWriteResGroup6], (instregex "OR(8|16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup6], (instregex "OR(8|16|32|64)rr")>;
-def: InstRW<[SBWriteResGroup6], (instregex "OR8i8")>;
+def: InstRW<[SBWriteResGroup6], (instregex "OR(8|16|32|64)i")>;
 def: InstRW<[SBWriteResGroup6], (instregex "PANDNrr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "PANDrr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "PORrr")>;
@@ -690,7 +690,7 @@ def: InstRW<[SBWriteResGroup6], (instregex "PXORrr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "STC")>;
 def: InstRW<[SBWriteResGroup6], (instregex "SUB(8|16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup6], (instregex "SUB(8|16|32|64)rr")>;
-def: InstRW<[SBWriteResGroup6], (instregex "SUB8i8")>;
+def: InstRW<[SBWriteResGroup6], (instregex "SUB(8|16|32|64)i")>;
 def: InstRW<[SBWriteResGroup6], (instregex "TEST(8|16|32|64)rr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "TEST8i8")>;
 def: InstRW<[SBWriteResGroup6], (instregex "TEST8ri")>;
@@ -702,7 +702,7 @@ def: InstRW<[SBWriteResGroup6], (instregex "VPORrr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "VPXORrr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "XOR(8|16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup6], (instregex "XOR(8|16|32|64)rr")>;
-def: InstRW<[SBWriteResGroup6], (instregex "XOR8i8")>;
+def: InstRW<[SBWriteResGroup6], (instregex "XOR(8|16|32|64)i")>;
 
 def SBWriteResGroup7 : SchedWriteRes<[SBPort0]> {
   let Latency = 2;
@@ -845,9 +845,11 @@ def SBWriteResGroup19 : SchedWriteRes<[SBPort05,SBPort015]> {
 }
 def: InstRW<[SBWriteResGroup19], (instregex "ADC(8|16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup19], (instregex "ADC(8|16|32|64)rr")>;
+def: InstRW<[SBWriteResGroup19], (instregex "ADC(8|16|32|64)i")>;
 def: InstRW<[SBWriteResGroup19], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr")>;
 def: InstRW<[SBWriteResGroup19], (instregex "SBB(8|16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup19], (instregex "SBB(8|16|32|64)rr")>;
+def: InstRW<[SBWriteResGroup19], (instregex "SBB(8|16|32|64)i")>;
 def: InstRW<[SBWriteResGroup19], (instregex "SHLD(16|32|64)rri8")>;
 def: InstRW<[SBWriteResGroup19], (instregex "SHRD(16|32|64)rri8")>;
 
@@ -1050,11 +1052,9 @@ def SBWriteResGroup25 : SchedWriteRes<[SBPort015]> {
   let NumMicroOps = 3;
   let ResourceCycles = [3];
 }
-def: InstRW<[SBWriteResGroup25], (instregex "ADC8i8")>;
 def: InstRW<[SBWriteResGroup25], (instregex "LEAVE64")>;
 def: InstRW<[SBWriteResGroup25], (instregex "OUT32rr")>;
 def: InstRW<[SBWriteResGroup25], (instregex "OUT8rr")>;
-def: InstRW<[SBWriteResGroup25], (instregex "SBB8i8")>;
 def: InstRW<[SBWriteResGroup25], (instregex "XADD(16|32|64)rr")>;
 def: InstRW<[SBWriteResGroup25], (instregex "XADD8rr")>;
 
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index d2e7def3e7e..0526a3023a4 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -703,6 +703,7 @@ def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
   let ResourceCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)i")>;
 def: InstRW<[SKLWriteResGroup7], (instregex "ADC(8|16|32|64)rr")>;
 def: InstRW<[SKLWriteResGroup7], (instregex "ADCX(32|64)rr")>;
 def: InstRW<[SKLWriteResGroup7], (instregex "ADOX(32|64)rr")>;
@@ -727,6 +728,7 @@ def: InstRW<[SKLWriteResGroup7], (instregex "SAR(8|16|32|64)r1")>;
 def: InstRW<[SKLWriteResGroup7], (instregex "SAR(8|16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup7], (instregex "SARX(32|64)rr")>;
 def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)ri")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)i")>;
 def: InstRW<[SKLWriteResGroup7], (instregex "SBB(8|16|32|64)rr")>;
 def: InstRW<[SKLWriteResGroup7], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r")>;
 def: InstRW<[SKLWriteResGroup7], (instregex "SHL(8|16|32|64)r1")>;
@@ -847,16 +849,16 @@ def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
 }
 def: InstRW<[SKLWriteResGroup10], (instregex "ADD(8|16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "ADD(8|16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "ADD8i8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "ADD(8|16|32|64)i")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "AND(8|16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "AND(8|16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "AND8i8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "AND(8|16|32|64)i")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "CBW")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "CLC")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "CMC")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "CMP(8|16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "CMP(8|16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "CMP8i8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "CMP(8|16|32|64)i")>;
 def: InstRW<[SKLWriteResGroup10], (instrs CWDE)>;
 def: InstRW<[SKLWriteResGroup10], (instregex "DEC(8|16|32|64)r")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "INC(8|16|32|64)r")>;
@@ -873,7 +875,7 @@ def: InstRW<[SKLWriteResGroup10], (instregex "NOOP")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "NOT(8|16|32|64)r")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "OR(8|16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "OR(8|16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "OR8i8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "OR(8|16|32|64)i")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "SAHF")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "SGDT64m")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "SIDT64m")>;
@@ -883,7 +885,7 @@ def: InstRW<[SKLWriteResGroup10], (instregex "STC")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "STRm")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "SUB(8|16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "SUB(8|16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "SUB8i8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "SUB(8|16|32|64)i")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "SYSCALL")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "TEST(8|16|32|64)rr")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "TEST8i8")>;
@@ -891,7 +893,7 @@ def: InstRW<[SKLWriteResGroup10], (instregex "TEST8ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "XOR(8|16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "XOR(8|16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "XOR8i8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "XOR(8|16|32|64)i")>;
 
 def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
   let Latency = 1;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index 627b7ce251a..16a10989c6a 100755
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -1007,6 +1007,7 @@ def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {
   let ResourceCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri")>;
+def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)i")>;
 def: InstRW<[SKXWriteResGroup7], (instregex "ADC(8|16|32|64)rr")>;
 def: InstRW<[SKXWriteResGroup7], (instregex "ADCX(32|64)rr")>;
 def: InstRW<[SKXWriteResGroup7], (instregex "ADOX(32|64)rr")>;
@@ -1031,6 +1032,7 @@ def: InstRW<[SKXWriteResGroup7], (instregex "SAR(8|16|32|64)r1")>;
 def: InstRW<[SKXWriteResGroup7], (instregex "SAR(8|16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup7], (instregex "SARX(32|64)rr")>;
 def: InstRW<[SKXWriteResGroup7], (instregex "SBB(16|32|64)ri")>;
+def: InstRW<[SKXWriteResGroup7], (instregex "SBB(16|32|64)i")>;
 def: InstRW<[SKXWriteResGroup7], (instregex "SBB(8|16|32|64)rr")>;
 def: InstRW<[SKXWriteResGroup7], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r")>;
 def: InstRW<[SKXWriteResGroup7], (instregex "SHL(8|16|32|64)r1")>;
@@ -1277,16 +1279,16 @@ def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
 }
 def: InstRW<[SKXWriteResGroup10], (instregex "ADD(8|16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "ADD(8|16|32|64)rr")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "ADD8i8")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "ADD(8|16|32|64)i")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "AND(8|16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "AND(8|16|32|64)rr")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "AND8i8")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "AND(8|16|32|64)i")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "CBW")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "CLC")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "CMC")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "CMP(8|16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "CMP(8|16|32|64)rr")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "CMP8i8")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "CMP(8|16|32|64)i")>;
 def: InstRW<[SKXWriteResGroup10], (instrs CWDE)>;
 def: InstRW<[SKXWriteResGroup10], (instregex "DEC(8|16|32|64)r")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "INC(8|16|32|64)r")>;
@@ -1303,7 +1305,7 @@ def: InstRW<[SKXWriteResGroup10], (instregex "NOOP")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "NOT(8|16|32|64)r")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "OR(8|16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "OR(8|16|32|64)rr")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "OR8i8")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "OR(8|16|32|64)i")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "SAHF")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "SGDT64m")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "SIDT64m")>;
@@ -1313,7 +1315,7 @@ def: InstRW<[SKXWriteResGroup10], (instregex "STC")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "STRm")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "SUB(8|16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "SUB(8|16|32|64)rr")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "SUB8i8")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "SUB(8|16|32|64)i")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "SYSCALL")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "TEST(8|16|32|64)rr")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "TEST8i8")>;
@@ -1321,7 +1323,7 @@ def: InstRW<[SKXWriteResGroup10], (instregex "TEST8ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "XOR(8|16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "XOR(8|16|32|64)rr")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "XOR8i8")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "XOR(8|16|32|64)i")>;
 
 def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {
   let Latency = 1;
diff --git a/llvm/test/CodeGen/X86/schedule-x86_64.ll b/llvm/test/CodeGen/X86/schedule-x86_64.ll
index 1f98ec6055e..72a764e64fa 100644
--- a/llvm/test/CodeGen/X86/schedule-x86_64.ll
+++ b/llvm/test/CodeGen/X86/schedule-x86_64.ll
@@ -15,7 +15,7 @@ define void @test_adc_8(i8 %a0, i8* %a1) optsize {
 ; GENERIC-LABEL: test_adc_8:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    #APP
-; GENERIC-NEXT:    adcb $7, %al # sched: [3:1.00]
+; GENERIC-NEXT:    adcb $7, %al # sched: [2:0.67]
 ; GENERIC-NEXT:    adcb $7, %dil # sched: [2:0.67]
 ; GENERIC-NEXT:    adcb $7, (%rsi) # sched: [9:1.00]
 ; GENERIC-NEXT:    adcb %dil, %dil # sched: [2:0.67]
@@ -51,7 +51,7 @@ define void @test_adc_8(i8 %a0, i8* %a1) optsize {
 ; SANDY-LABEL: test_adc_8:
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    #APP
-; SANDY-NEXT:    adcb $7, %al # sched: [3:1.00]
+; SANDY-NEXT:    adcb $7, %al # sched: [2:0.67]
 ; SANDY-NEXT:    adcb $7, %dil # sched: [2:0.67]
 ; SANDY-NEXT:    adcb $7, (%rsi) # sched: [9:1.00]
 ; SANDY-NEXT:    adcb %dil, %dil # sched: [2:0.67]
@@ -139,7 +139,7 @@ define void @test_adc_16(i16 %a0, i16* %a1) optsize {
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    #APP
 ; GENERIC-NEXT:    adcw $511, %ax # imm = 0x1FF
-; GENERIC-NEXT:    # sched: [1:0.33]
+; GENERIC-NEXT:    # sched: [2:0.67]
 ; GENERIC-NEXT:    adcw $511, %di # imm = 0x1FF
 ; GENERIC-NEXT:    # sched: [2:0.67]
 ; GENERIC-NEXT:    adcw $511, (%rsi) # imm = 0x1FF
@@ -190,7 +190,7 @@ define void @test_adc_16(i16 %a0, i16* %a1) optsize {
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    #APP
 ; SANDY-NEXT:    adcw $511, %ax # imm = 0x1FF
-; SANDY-NEXT:    # sched: [1:0.33]
+; SANDY-NEXT:    # sched: [2:0.67]
 ; SANDY-NEXT:    adcw $511, %di # imm = 0x1FF
 ; SANDY-NEXT:    # sched: [2:0.67]
 ; SANDY-NEXT:    adcw $511, (%rsi) # imm = 0x1FF
@@ -207,7 +207,7 @@ define void @test_adc_16(i16 %a0, i16* %a1) optsize {
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
 ; HASWELL-NEXT:    adcw $511, %ax # imm = 0x1FF
-; HASWELL-NEXT:    # sched: [1:0.25]
+; HASWELL-NEXT:    # sched: [2:0.50]
 ; HASWELL-NEXT:    adcw $511, %di # imm = 0x1FF
 ; HASWELL-NEXT:    # sched: [2:0.50]
 ; HASWELL-NEXT:    adcw $511, (%rsi) # imm = 0x1FF
@@ -224,7 +224,7 @@ define void @test_adc_16(i16 %a0, i16* %a1) optsize {
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    #APP
 ; BROADWELL-NEXT:    adcw $511, %ax # imm = 0x1FF
-; BROADWELL-NEXT:    # sched: [1:0.25]
+; BROADWELL-NEXT:    # sched: [1:0.50]
 ; BROADWELL-NEXT:    adcw $511, %di # imm = 0x1FF
 ; BROADWELL-NEXT:    # sched: [1:0.50]
 ; BROADWELL-NEXT:    adcw $511, (%rsi) # imm = 0x1FF
@@ -241,7 +241,7 @@ define void @test_adc_16(i16 %a0, i16* %a1) optsize {
 ; SKYLAKE:       # %bb.0:
 ; SKYLAKE-NEXT:    #APP
 ; SKYLAKE-NEXT:    adcw $511, %ax # imm = 0x1FF
-; SKYLAKE-NEXT:    # sched: [1:0.25]
+; SKYLAKE-NEXT:    # sched: [1:0.50]
 ; SKYLAKE-NEXT:    adcw $511, %di # imm = 0x1FF
 ; SKYLAKE-NEXT:    # sched: [1:0.50]
 ; SKYLAKE-NEXT:    adcw $511, (%rsi) # imm = 0x1FF
@@ -258,7 +258,7 @@ define void @test_adc_16(i16 %a0, i16* %a1) optsize {
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    #APP
 ; SKX-NEXT:    adcw $511, %ax # imm = 0x1FF
-; SKX-NEXT:    # sched: [1:0.25]
+; SKX-NEXT:    # sched: [1:0.50]
 ; SKX-NEXT:    adcw $511, %di # imm = 0x1FF
 ; SKX-NEXT:    # sched: [1:0.50]
 ; SKX-NEXT:    adcw $511, (%rsi) # imm = 0x1FF
@@ -312,7 +312,7 @@ define void @test_adc_32(i32 %a0, i32* %a1) optsize {
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    #APP
 ; GENERIC-NEXT:    adcl $665536, %eax # imm = 0xA27C0
-; GENERIC-NEXT:    # sched: [1:0.33]
+; GENERIC-NEXT:    # sched: [2:0.67]
 ; GENERIC-NEXT:    adcl $665536, %edi # imm = 0xA27C0
 ; GENERIC-NEXT:    # sched: [2:0.67]
 ; GENERIC-NEXT:    adcl $665536, (%rsi) # imm = 0xA27C0
@@ -363,7 +363,7 @@ define void @test_adc_32(i32 %a0, i32* %a1) optsize {
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    #APP
 ; SANDY-NEXT:    adcl $665536, %eax # imm = 0xA27C0
-; SANDY-NEXT:    # sched: [1:0.33]
+; SANDY-NEXT:    # sched: [2:0.67]
 ; SANDY-NEXT:    adcl $665536, %edi # imm = 0xA27C0
 ; SANDY-NEXT:    # sched: [2:0.67]
 ; SANDY-NEXT:    adcl $665536, (%rsi) # imm = 0xA27C0
@@ -380,7 +380,7 @@ define void @test_adc_32(i32 %a0, i32* %a1) optsize {
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
 ; HASWELL-NEXT:    adcl $665536, %eax # imm = 0xA27C0
-; HASWELL-NEXT:    # sched: [1:0.25]
+; HASWELL-NEXT:    # sched: [2:0.50]
 ; HASWELL-NEXT:    adcl $665536, %edi # imm = 0xA27C0
 ; HASWELL-NEXT:    # sched: [2:0.50]
 ; HASWELL-NEXT:    adcl $665536, (%rsi) # imm = 0xA27C0
@@ -397,7 +397,7 @@ define void @test_adc_32(i32 %a0, i32* %a1) optsize {
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    #APP
 ; BROADWELL-NEXT:    adcl $665536, %eax # imm = 0xA27C0
-; BROADWELL-NEXT:    # sched: [1:0.25]
+; BROADWELL-NEXT:    # sched: [1:0.50]
 ; BROADWELL-NEXT:    adcl $665536, %edi # imm = 0xA27C0
 ; BROADWELL-NEXT:    # sched: [1:0.50]
 ; BROADWELL-NEXT:    adcl $665536, (%rsi) # imm = 0xA27C0
@@ -414,7 +414,7 @@ define void @test_adc_32(i32 %a0, i32* %a1) optsize {
 ; SKYLAKE:       # %bb.0:
 ; SKYLAKE-NEXT:    #APP
 ; SKYLAKE-NEXT:    adcl $665536, %eax # imm = 0xA27C0
-; SKYLAKE-NEXT:    # sched: [1:0.25]
+; SKYLAKE-NEXT:    # sched: [1:0.50]
 ; SKYLAKE-NEXT:    adcl $665536, %edi # imm = 0xA27C0
 ; SKYLAKE-NEXT:    # sched: [1:0.50]
 ; SKYLAKE-NEXT:    adcl $665536, (%rsi) # imm = 0xA27C0
@@ -431,7 +431,7 @@ define void @test_adc_32(i32 %a0, i32* %a1) optsize {
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    #APP
 ; SKX-NEXT:    adcl $665536, %eax # imm = 0xA27C0
-; SKX-NEXT:    # sched: [1:0.25]
+; SKX-NEXT:    # sched: [1:0.50]
 ; SKX-NEXT:    adcl $665536, %edi # imm = 0xA27C0
 ; SKX-NEXT:    # sched: [1:0.50]
 ; SKX-NEXT:    adcl $665536, (%rsi) # imm = 0xA27C0
@@ -485,7 +485,7 @@ define void @test_adc_64(i64 %a0, i64* %a1) optsize {
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    #APP
 ; GENERIC-NEXT:    adcq $665536, %rax # imm = 0xA27C0
-; GENERIC-NEXT:    # sched: [1:0.33]
+; GENERIC-NEXT:    # sched: [2:0.67]
 ; GENERIC-NEXT:    adcq $665536, %rdi # imm = 0xA27C0
 ; GENERIC-NEXT:    # sched: [2:0.67]
 ; GENERIC-NEXT:    adcq $665536, (%rsi) # imm = 0xA27C0
@@ -536,7 +536,7 @@ define void @test_adc_64(i64 %a0, i64* %a1) optsize {
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    #APP
 ; SANDY-NEXT:    adcq $665536, %rax # imm = 0xA27C0
-; SANDY-NEXT:    # sched: [1:0.33]
+; SANDY-NEXT:    # sched: [2:0.67]
 ; SANDY-NEXT:    adcq $665536, %rdi # imm = 0xA27C0
 ; SANDY-NEXT:    # sched: [2:0.67]
 ; SANDY-NEXT:    adcq $665536, (%rsi) # imm = 0xA27C0
@@ -553,7 +553,7 @@ define void @test_adc_64(i64 %a0, i64* %a1) optsize {
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
 ; HASWELL-NEXT:    adcq $665536, %rax # imm = 0xA27C0
-; HASWELL-NEXT:    # sched: [1:0.25]
+; HASWELL-NEXT:    # sched: [2:0.50]
 ; HASWELL-NEXT:    adcq $665536, %rdi # imm = 0xA27C0
 ; HASWELL-NEXT:    # sched: [2:0.50]
 ; HASWELL-NEXT:    adcq $665536, (%rsi) # imm = 0xA27C0
@@ -570,7 +570,7 @@ define void @test_adc_64(i64 %a0, i64* %a1) optsize {
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    #APP
 ; BROADWELL-NEXT:    adcq $665536, %rax # imm = 0xA27C0
-; BROADWELL-NEXT:    # sched: [1:0.25]
+; BROADWELL-NEXT:    # sched: [1:0.50]
 ; BROADWELL-NEXT:    adcq $665536, %rdi # imm = 0xA27C0
 ; BROADWELL-NEXT:    # sched: [1:0.50]
 ; BROADWELL-NEXT:    adcq $665536, (%rsi) # imm = 0xA27C0
@@ -587,7 +587,7 @@ define void @test_adc_64(i64 %a0, i64* %a1) optsize {
 ; SKYLAKE:       # %bb.0:
 ; SKYLAKE-NEXT:    #APP
 ; SKYLAKE-NEXT:    adcq $665536, %rax # imm = 0xA27C0
-; SKYLAKE-NEXT:    # sched: [1:0.25]
+; SKYLAKE-NEXT:    # sched: [1:0.50]
 ; SKYLAKE-NEXT:    adcq $665536, %rdi # imm = 0xA27C0
 ; SKYLAKE-NEXT:    # sched: [1:0.50]
 ; SKYLAKE-NEXT:    adcq $665536, (%rsi) # imm = 0xA27C0
@@ -604,7 +604,7 @@ define void @test_adc_64(i64 %a0, i64* %a1) optsize {
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    #APP
 ; SKX-NEXT:    adcq $665536, %rax # imm = 0xA27C0
-; SKX-NEXT:    # sched: [1:0.25]
+; SKX-NEXT:    # sched: [1:0.50]
 ; SKX-NEXT:    adcq $665536, %rdi # imm = 0xA27C0
 ; SKX-NEXT:    # sched: [1:0.50]
 ; SKX-NEXT:    adcq $665536, (%rsi) # imm = 0xA27C0
@@ -12777,7 +12777,7 @@ define void @test_sbb_8(i8 %a0, i8* %a1) optsize {
 ; GENERIC-LABEL: test_sbb_8:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    #APP
-; GENERIC-NEXT:    sbbb $7, %al # sched: [3:1.00]
+; GENERIC-NEXT:    sbbb $7, %al # sched: [2:0.67]
 ; GENERIC-NEXT:    sbbb $7, %dil # sched: [2:0.67]
 ; GENERIC-NEXT:    sbbb $7, (%rsi) # sched: [9:1.00]
 ; GENERIC-NEXT:    sbbb %dil, %dil # sched: [2:0.67]
@@ -12813,7 +12813,7 @@ define void @test_sbb_8(i8 %a0, i8* %a1) optsize {
 ; SANDY-LABEL: test_sbb_8:
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    #APP
-; SANDY-NEXT:    sbbb $7, %al # sched: [3:1.00]
+; SANDY-NEXT:    sbbb $7, %al # sched: [2:0.67]
 ; SANDY-NEXT:    sbbb $7, %dil # sched: [2:0.67]
 ; SANDY-NEXT:    sbbb $7, (%rsi) # sched: [9:1.00]
 ; SANDY-NEXT:    sbbb %dil, %dil # sched: [2:0.67]
@@ -12901,7 +12901,7 @@ define void @test_sbb_16(i16 %a0, i16* %a1) optsize {
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    #APP
 ; GENERIC-NEXT:    sbbw $511, %ax # imm = 0x1FF
-; GENERIC-NEXT:    # sched: [1:0.33]
+; GENERIC-NEXT:    # sched: [2:0.67]
 ; GENERIC-NEXT:    sbbw $511, %di # imm = 0x1FF
 ; GENERIC-NEXT:    # sched: [2:0.67]
 ; GENERIC-NEXT:    sbbw $511, (%rsi) # imm = 0x1FF
@@ -12952,7 +12952,7 @@ define void @test_sbb_16(i16 %a0, i16* %a1) optsize {
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    #APP
 ; SANDY-NEXT:    sbbw $511, %ax # imm = 0x1FF
-; SANDY-NEXT:    # sched: [1:0.33]
+; SANDY-NEXT:    # sched: [2:0.67]
 ; SANDY-NEXT:    sbbw $511, %di # imm = 0x1FF
 ; SANDY-NEXT:    # sched: [2:0.67]
 ; SANDY-NEXT:    sbbw $511, (%rsi) # imm = 0x1FF
@@ -12969,7 +12969,7 @@ define void @test_sbb_16(i16 %a0, i16* %a1) optsize {
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
 ; HASWELL-NEXT:    sbbw $511, %ax # imm = 0x1FF
-; HASWELL-NEXT:    # sched: [1:0.25]
+; HASWELL-NEXT:    # sched: [2:0.50]
 ; HASWELL-NEXT:    sbbw $511, %di # imm = 0x1FF
 ; HASWELL-NEXT:    # sched: [2:0.50]
 ; HASWELL-NEXT:    sbbw $511, (%rsi) # imm = 0x1FF
@@ -12986,7 +12986,7 @@ define void @test_sbb_16(i16 %a0, i16* %a1) optsize {
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    #APP
 ; BROADWELL-NEXT:    sbbw $511, %ax # imm = 0x1FF
-; BROADWELL-NEXT:    # sched: [1:0.25]
+; BROADWELL-NEXT:    # sched: [1:0.50]
 ; BROADWELL-NEXT:    sbbw $511, %di # imm = 0x1FF
 ; BROADWELL-NEXT:    # sched: [1:0.50]
 ; BROADWELL-NEXT:    sbbw $511, (%rsi) # imm = 0x1FF
@@ -13003,7 +13003,7 @@ define void @test_sbb_16(i16 %a0, i16* %a1) optsize {
 ; SKYLAKE:       # %bb.0:
 ; SKYLAKE-NEXT:    #APP
 ; SKYLAKE-NEXT:    sbbw $511, %ax # imm = 0x1FF
-; SKYLAKE-NEXT:    # sched: [1:0.25]
+; SKYLAKE-NEXT:    # sched: [1:0.50]
 ; SKYLAKE-NEXT:    sbbw $511, %di # imm = 0x1FF
 ; SKYLAKE-NEXT:    # sched: [1:0.50]
 ; SKYLAKE-NEXT:    sbbw $511, (%rsi) # imm = 0x1FF
@@ -13020,7 +13020,7 @@ define void @test_sbb_16(i16 %a0, i16* %a1) optsize {
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    #APP
 ; SKX-NEXT:    sbbw $511, %ax # imm = 0x1FF
-; SKX-NEXT:    # sched: [1:0.25]
+; SKX-NEXT:    # sched: [1:0.50]
 ; SKX-NEXT:    sbbw $511, %di # imm = 0x1FF
 ; SKX-NEXT:    # sched: [1:0.50]
 ; SKX-NEXT:    sbbw $511, (%rsi) # imm = 0x1FF
@@ -13074,7 +13074,7 @@ define void @test_sbb_32(i32 %a0, i32* %a1) optsize {
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    #APP
 ; GENERIC-NEXT:    sbbl $665536, %eax # imm = 0xA27C0
-; GENERIC-NEXT:    # sched: [1:0.33]
+; GENERIC-NEXT:    # sched: [2:0.67]
 ; GENERIC-NEXT:    sbbl $665536, %edi # imm = 0xA27C0
 ; GENERIC-NEXT:    # sched: [2:0.67]
 ; GENERIC-NEXT:    sbbl $665536, (%rsi) # imm = 0xA27C0
@@ -13125,7 +13125,7 @@ define void @test_sbb_32(i32 %a0, i32* %a1) optsize {
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    #APP
 ; SANDY-NEXT:    sbbl $665536, %eax # imm = 0xA27C0
-; SANDY-NEXT:    # sched: [1:0.33]
+; SANDY-NEXT:    # sched: [2:0.67]
 ; SANDY-NEXT:    sbbl $665536, %edi # imm = 0xA27C0
 ; SANDY-NEXT:    # sched: [2:0.67]
 ; SANDY-NEXT:    sbbl $665536, (%rsi) # imm = 0xA27C0
@@ -13142,7 +13142,7 @@ define void @test_sbb_32(i32 %a0, i32* %a1) optsize {
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
 ; HASWELL-NEXT:    sbbl $665536, %eax # imm = 0xA27C0
-; HASWELL-NEXT:    # sched: [1:0.25]
+; HASWELL-NEXT:    # sched: [2:0.50]
 ; HASWELL-NEXT:    sbbl $665536, %edi # imm = 0xA27C0
 ; HASWELL-NEXT:    # sched: [2:0.50]
 ; HASWELL-NEXT:    sbbl $665536, (%rsi) # imm = 0xA27C0
@@ -13159,7 +13159,7 @@ define void @test_sbb_32(i32 %a0, i32* %a1) optsize {
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    #APP
 ; BROADWELL-NEXT:    sbbl $665536, %eax # imm = 0xA27C0
-; BROADWELL-NEXT:    # sched: [1:0.25]
+; BROADWELL-NEXT:    # sched: [1:0.50]
 ; BROADWELL-NEXT:    sbbl $665536, %edi # imm = 0xA27C0
 ; BROADWELL-NEXT:    # sched: [1:0.50]
 ; BROADWELL-NEXT:    sbbl $665536, (%rsi) # imm = 0xA27C0
@@ -13176,7 +13176,7 @@ define void @test_sbb_32(i32 %a0, i32* %a1) optsize {
 ; SKYLAKE:       # %bb.0:
 ; SKYLAKE-NEXT:    #APP
 ; SKYLAKE-NEXT:    sbbl $665536, %eax # imm = 0xA27C0
-; SKYLAKE-NEXT:    # sched: [1:0.25]
+; SKYLAKE-NEXT:    # sched: [1:0.50]
 ; SKYLAKE-NEXT:    sbbl $665536, %edi # imm = 0xA27C0
 ; SKYLAKE-NEXT:    # sched: [1:0.50]
 ; SKYLAKE-NEXT:    sbbl $665536, (%rsi) # imm = 0xA27C0
@@ -13193,7 +13193,7 @@ define void @test_sbb_32(i32 %a0, i32* %a1) optsize {
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    #APP
 ; SKX-NEXT:    sbbl $665536, %eax # imm = 0xA27C0
-; SKX-NEXT:    # sched: [1:0.25]
+; SKX-NEXT:    # sched: [1:0.50]
 ; SKX-NEXT:    sbbl $665536, %edi # imm = 0xA27C0
 ; SKX-NEXT:    # sched: [1:0.50]
 ; SKX-NEXT:    sbbl $665536, (%rsi) # imm = 0xA27C0
@@ -13247,7 +13247,7 @@ define void @test_sbb_64(i64 %a0, i64* %a1) optsize {
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    #APP
 ; GENERIC-NEXT:    sbbq $665536, %rax # imm = 0xA27C0
-; GENERIC-NEXT:    # sched: [1:0.33]
+; GENERIC-NEXT:    # sched: [2:0.67]
 ; GENERIC-NEXT:    sbbq $665536, %rdi # imm = 0xA27C0
 ; GENERIC-NEXT:    # sched: [2:0.67]
 ; GENERIC-NEXT:    sbbq $665536, (%rsi) # imm = 0xA27C0
@@ -13298,7 +13298,7 @@ define void @test_sbb_64(i64 %a0, i64* %a1) optsize {
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    #APP
 ; SANDY-NEXT:    sbbq $665536, %rax # imm = 0xA27C0
-; SANDY-NEXT:    # sched: [1:0.33]
+; SANDY-NEXT:    # sched: [2:0.67]
 ; SANDY-NEXT:    sbbq $665536, %rdi # imm = 0xA27C0
 ; SANDY-NEXT:    # sched: [2:0.67]
 ; SANDY-NEXT:    sbbq $665536, (%rsi) # imm = 0xA27C0
@@ -13315,7 +13315,7 @@ define void @test_sbb_64(i64 %a0, i64* %a1) optsize {
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    #APP
 ; HASWELL-NEXT:    sbbq $665536, %rax # imm = 0xA27C0
-; HASWELL-NEXT:    # sched: [1:0.25]
+; HASWELL-NEXT:    # sched: [2:0.50]
 ; HASWELL-NEXT:    sbbq $665536, %rdi # imm = 0xA27C0
 ; HASWELL-NEXT:    # sched: [2:0.50]
 ; HASWELL-NEXT:    sbbq $665536, (%rsi) # imm = 0xA27C0
@@ -13332,7 +13332,7 @@ define void @test_sbb_64(i64 %a0, i64* %a1) optsize {
 ; BROADWELL:       # %bb.0:
 ; BROADWELL-NEXT:    #APP
 ; BROADWELL-NEXT:    sbbq $665536, %rax # imm = 0xA27C0
-; BROADWELL-NEXT:    # sched: [1:0.25]
+; BROADWELL-NEXT:    # sched: [1:0.50]
 ; BROADWELL-NEXT:    sbbq $665536, %rdi # imm = 0xA27C0
 ; BROADWELL-NEXT:    # sched: [1:0.50]
 ; BROADWELL-NEXT:    sbbq $665536, (%rsi) # imm = 0xA27C0
@@ -13349,7 +13349,7 @@ define void @test_sbb_64(i64 %a0, i64* %a1) optsize {
 ; SKYLAKE:       # %bb.0:
 ; SKYLAKE-NEXT:    #APP
 ; SKYLAKE-NEXT:    sbbq $665536, %rax # imm = 0xA27C0
-; SKYLAKE-NEXT:    # sched: [1:0.25]
+; SKYLAKE-NEXT:    # sched: [1:0.50]
 ; SKYLAKE-NEXT:    sbbq $665536, %rdi # imm = 0xA27C0
 ; SKYLAKE-NEXT:    # sched: [1:0.50]
 ; SKYLAKE-NEXT:    sbbq $665536, (%rsi) # imm = 0xA27C0
@@ -13366,7 +13366,7 @@ define void @test_sbb_64(i64 %a0, i64* %a1) optsize {
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    #APP
 ; SKX-NEXT:    sbbq $665536, %rax # imm = 0xA27C0
-; SKX-NEXT:    # sched: [1:0.25]
+; SKX-NEXT:    # sched: [1:0.50]
 ; SKX-NEXT:    sbbq $665536, %rdi # imm = 0xA27C0
 ; SKX-NEXT:    # sched: [1:0.50]
 ; SKX-NEXT:    sbbq $665536, (%rsi) # imm = 0xA27C0