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| author | Craig Topper <craig.topper@intel.com> | 2019-09-19 06:27:12 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-09-19 06:27:12 +0000 |
| commit | d103bb654fe1e7adf60b085c295a38b182859a7d (patch) | |
| tree | ea2f6809eb5476616c333a3183e4c179ed71978c | |
| parent | eff4fd69998217837ba8b1d7a2e0394d21e34949 (diff) | |
| download | bcm5719-llvm-d103bb654fe1e7adf60b085c295a38b182859a7d.tar.gz bcm5719-llvm-d103bb654fe1e7adf60b085c295a38b182859a7d.zip | |
[X86] Change a SmallVector& argument to SmallVectorImpl&. NFC
Avoids repeating the size.
llvm-svn: 372302
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index b03ef0d0640..a41cde23785 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -2493,7 +2493,7 @@ static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc, /// Breaks v64i1 value into two registers and adds the new node to the DAG static void Passv64i1ArgInRegs( const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg, - SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, CCValAssign &VA, + SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, const X86Subtarget &Subtarget) { assert(Subtarget.hasBWI() && "Expected AVX512BW target!"); assert(Subtarget.is32Bit() && "Expecting 32 bit target"); |
