diff options
| author | Johnny Chen <johnny.chen@apple.com> | 2011-04-13 21:59:01 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-13 21:59:01 +0000 |
| commit | d0fb04f4372c3fdb86bcb5f4fccfa720f17d8114 (patch) | |
| tree | d49604899f841e8eafd0e72648041d4098254cb4 | |
| parent | 13b5a2c2f80a7a4f3e77987ffb0e00467f5600bc (diff) | |
| download | bcm5719-llvm-d0fb04f4372c3fdb86bcb5f4fccfa720f17d8114.tar.gz bcm5719-llvm-d0fb04f4372c3fdb86bcb5f4fccfa720f17d8114.zip | |
Thumb disassembler did not handle tBRIND (indirect branch) properly.
rdar://problem/9280370
llvm-svn: 129480
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h | 16 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/thumb-tests.txt | 3 |
2 files changed, 13 insertions, 6 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h index ec8005627e1..aded43b4b7f 100644 --- a/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h +++ b/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h @@ -479,6 +479,7 @@ static bool DisassembleThumb1DP(MCInst &MI, unsigned Opcode, uint32_t insn, // tBX_RET: 0 operand // tBX_RET_vararg: Rm // tBLXr_r9: Rm +// tBRIND: Rm static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { @@ -486,14 +487,17 @@ static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn, if (NumOps == 0) return true; - // BX/BLX has 1 reg operand: Rm. - if (Opcode == ARM::tBLXr_r9 || Opcode == ARM::tBX_Rm) { - // Handling the two predicate operands before the reg operand. - if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps)) - return false; + // BX/BLX/tBRIND (indirect branch, i.e, mov pc, Rm) has 1 reg operand: Rm. + if (Opcode==ARM::tBLXr_r9 || Opcode==ARM::tBX_Rm || Opcode==ARM::tBRIND) { + if (Opcode != ARM::tBRIND) { + // Handling the two predicate operands before the reg operand. + if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps)) + return false; + NumOpsAdded += 2; + } MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, getT1Rm(insn)))); - NumOpsAdded = 3; + NumOpsAdded += 1; return true; } diff --git a/llvm/test/MC/Disassembler/ARM/thumb-tests.txt b/llvm/test/MC/Disassembler/ARM/thumb-tests.txt index 04bde41af62..a30422626fc 100644 --- a/llvm/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/llvm/test/MC/Disassembler/ARM/thumb-tests.txt @@ -244,3 +244,6 @@ # CHECK: mov.w r3, #4294967295 0x4f 0xf0 0xff 0x33 + +# CHECK: mov pc, sp +0xef 0x46 |
