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| author | Craig Topper <craig.topper@intel.com> | 2018-01-07 06:24:30 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-01-07 06:24:30 +0000 |
| commit | d0859a03b560629f58498d1346e1c47ae32c6cc1 (patch) | |
| tree | d8e85b0d69cd31d3c48c62db1fb023141eeae23a | |
| parent | aa739411765ed97ebf818eb556eafce4d1055891 (diff) | |
| download | bcm5719-llvm-d0859a03b560629f58498d1346e1c47ae32c6cc1.tar.gz bcm5719-llvm-d0859a03b560629f58498d1346e1c47ae32c6cc1.zip | |
[X86] Correct the load folding flags for xmm fp->mmx conversion instructions.
The instructions that load 64-bits or an xmm register should be TB_NO_REVERSE to avoid the load being widened during unfold. The instructions that load 128-bits need to ensure 128-bit alignment.
llvm-svn: 321956
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 03ffe82da5d..92b3f311db9 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -672,11 +672,11 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::UCOMISSrr, X86::UCOMISSrm, 0 }, // MMX version of foldable instructions - { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 }, + { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, TB_ALIGN_16 }, { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 }, - { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 }, - { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 }, - { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 }, + { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, TB_NO_REVERSE }, + { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, TB_ALIGN_16 }, + { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, TB_NO_REVERSE }, { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 }, { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 }, { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 }, |
