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| author | Bill Wendling <isanbard@gmail.com> | 2011-10-20 20:37:11 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2011-10-20 20:37:11 +0000 |
| commit | cf7bdf4438b2b1f6fedece6e955def61cc80fb8d (patch) | |
| tree | c54bfb8764270ae2e5a8712d5c9ace145b657c84 | |
| parent | f105192ad5115946a4054004f56da09a9123902b (diff) | |
| download | bcm5719-llvm-cf7bdf4438b2b1f6fedece6e955def61cc80fb8d.tar.gz bcm5719-llvm-cf7bdf4438b2b1f6fedece6e955def61cc80fb8d.zip | |
Add missing operand. <rdar://problem/10313323>
llvm-svn: 142615
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 34023af084a..7df743b750d 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -5924,7 +5924,8 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const { unsigned VReg1 = MRI->createVirtualRegister(TRC); AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp)) .addReg(VReg1, RegState::Define) - .addConstantPoolIndex(Idx)); + .addConstantPoolIndex(Idx) + .addImm(0)); AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr)) .addReg(NewVReg1) .addReg(VReg1, RegState::Kill)); |
