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| author | Chad Rosier <mcrosier@codeaurora.org> | 2016-03-21 18:04:10 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@codeaurora.org> | 2016-03-21 18:04:10 +0000 |
| commit | cf173ffb46456155191f461580732262dcf3c969 (patch) | |
| tree | e89b6ea33df6387732650d9c4ca49702a7222c45 | |
| parent | cb38a6bd35b2ef94ef675ba1dccd00ad6bfac281 (diff) | |
| download | bcm5719-llvm-cf173ffb46456155191f461580732262dcf3c969.tar.gz bcm5719-llvm-cf173ffb46456155191f461580732262dcf3c969.zip | |
[AArch64] Add a helpful assert. NFC.
llvm-svn: 263965
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index d447a721c72..43db52fd082 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -1402,6 +1402,7 @@ bool AArch64InstrInfo::getMemOpBaseRegImmOfs( bool AArch64InstrInfo::getMemOpBaseRegImmOfsWidth( MachineInstr *LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const { + assert(LdSt->mayLoadOrStore() && "Expected a memory operation."); // Handle only loads/stores with base register followed by immediate offset. if (LdSt->getNumOperands() != 3) return false; |
