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author | Michael Liao <michael.liao@intel.com> | 2012-10-17 03:59:18 +0000 |
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committer | Michael Liao <michael.liao@intel.com> | 2012-10-17 03:59:18 +0000 |
commit | cef9541dac8ced74a037719a1770a93da8dbcfbc (patch) | |
tree | f657f919af38c763e450fc2612a5a74476d2501d | |
parent | e68b8f4dcc2b3a6ab03326ad4167f1164cae61e4 (diff) | |
download | bcm5719-llvm-cef9541dac8ced74a037719a1770a93da8dbcfbc.tar.gz bcm5719-llvm-cef9541dac8ced74a037719a1770a93da8dbcfbc.zip |
Check SSSE3 instead of SSE4.1
- All shuffle insns required, especially PSHUB, are added in SSSE3.
llvm-svn: 166086
-rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index fb0fdb3631d..a205aef7427 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -15477,11 +15477,11 @@ static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, ISD::LoadExtType Ext = Ld->getExtensionType(); // If this is a vector EXT Load then attempt to optimize it using a - // shuffle. We need SSE4 for the shuffles. + // shuffle. We need SSSE3 shuffles. // TODO: It is possible to support ZExt by zeroing the undef values // during the shuffle phase or after the shuffle. if (RegVT.isVector() && RegVT.isInteger() && - Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { + Ext == ISD::EXTLOAD && Subtarget->hasSSSE3()) { assert(MemVT != RegVT && "Cannot extend to the same type"); assert(MemVT.isVector() && "Must load a vector from memory"); |