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authorSimon Pilgrim <llvm-dev@redking.me.uk>2017-10-22 18:38:57 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2017-10-22 18:38:57 +0000
commitce55eab9360ebc0482677ad7ea7602fba2a11954 (patch)
tree56c1c4156e8e24e449b5b9dcf3d8285b53063344
parentf9371d821f744afd6680a26254d62cf44586912d (diff)
downloadbcm5719-llvm-ce55eab9360ebc0482677ad7ea7602fba2a11954.tar.gz
bcm5719-llvm-ce55eab9360ebc0482677ad7ea7602fba2a11954.zip
Strip trailing whitespace. NFCI.
llvm-svn: 316296
-rw-r--r--llvm/lib/Target/X86/X86InstrAVX512.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 4f88d88385a..8f3d7a7bd1d 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -1222,7 +1222,7 @@ multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
(_.VT (OpNode SrcRC:$src))>, T8PD, EVEX;
}
-multiclass avx512_int_broadcastbw_reg<bits<8> opc, string Name,
+multiclass avx512_int_broadcastbw_reg<bits<8> opc, string Name,
X86VectorVTInfo _, SDPatternOperator OpNode,
RegisterClass SrcRC, SubRegIndex Subreg> {
let hasSideEffects = 0, ExeDomain = _.ExeDomain in
@@ -1250,7 +1250,7 @@ multiclass avx512_int_broadcastbw_reg_vl<bits<8> opc, string Name,
AVX512VLVectorVTInfo _, SDPatternOperator OpNode,
RegisterClass SrcRC, SubRegIndex Subreg, Predicate prd> {
let Predicates = [prd] in
- defm Z : avx512_int_broadcastbw_reg<opc, Name#Z, _.info512, OpNode, SrcRC,
+ defm Z : avx512_int_broadcastbw_reg<opc, Name#Z, _.info512, OpNode, SrcRC,
Subreg>, EVEX_V512;
let Predicates = [prd, HasVLX] in {
defm Z256 : avx512_int_broadcastbw_reg<opc, Name#Z256, _.info256, OpNode,
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