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author | Sanjay Patel <spatel@rotateright.com> | 2018-05-16 14:38:07 +0000 |
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committer | Sanjay Patel <spatel@rotateright.com> | 2018-05-16 14:38:07 +0000 |
commit | cda77b30e5efc10571d0e9528b5a43ee541d40c5 (patch) | |
tree | 623607e3ed1680033989f09d1283049c17dace2a | |
parent | bbc4e9a4e34d7bf250132d210f46bf943bf2f924 (diff) | |
download | bcm5719-llvm-cda77b30e5efc10571d0e9528b5a43ee541d40c5.tar.gz bcm5719-llvm-cda77b30e5efc10571d0e9528b5a43ee541d40c5.zip |
[OpenCL] make test independent of optimizer
There shouldn't be any tests that run the entire optimizer here,
but the last test in this file is definitely going to break with
a change in LLVM IR canonicalization. Change that part to check
the unoptimized IR because that's the real intent of this file.
llvm-svn: 332473
-rw-r--r-- | clang/test/CodeGenOpenCL/shifts.cl | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/clang/test/CodeGenOpenCL/shifts.cl b/clang/test/CodeGenOpenCL/shifts.cl index 14cd7aff65b..7011a4234bb 100644 --- a/clang/test/CodeGenOpenCL/shifts.cl +++ b/clang/test/CodeGenOpenCL/shifts.cl @@ -58,16 +58,17 @@ int4 vectorVectorTest(int4 a,int4 b) { return f; } -//OPT: @vectorScalarTest +//NOOPT-LABEL: @vectorScalarTest int4 vectorScalarTest(int4 a,int b) { - //OPT: [[SP0:%.+]] = insertelement <4 x i32> undef, i32 %b, i32 0 - //OPT: [[SP1:%.+]] = shufflevector <4 x i32> [[SP0]], <4 x i32> undef, <4 x i32> zeroinitializer - //OPT: [[VSM:%.+]] = and <4 x i32> [[SP1]], <i32 31, i32 31, i32 31, i32 31> - //OPT-NEXT: [[VSC:%.+]] = shl <4 x i32> %a, [[VSM]] + //NOOPT: [[SP0:%.+]] = insertelement <4 x i32> undef + //NOOPT: [[SP1:%.+]] = shufflevector <4 x i32> [[SP0]], <4 x i32> undef, <4 x i32> zeroinitializer + //NOOPT: [[VSM:%.+]] = and <4 x i32> [[SP1]], <i32 31, i32 31, i32 31, i32 31> + //NOOPT: [[VSC:%.+]] = shl <4 x i32> [[VSS:%.+]], [[VSM]] int4 c = a << b; - //OPT-NEXT: [[VSF:%.+]] = add <4 x i32> [[VSC]], <i32 4, i32 4, i32 4, i32 4> + //NOOPT: [[VSF:%.+]] = shl <4 x i32> [[VSC1:%.+]], <i32 2, i32 2, i32 2, i32 2> + //NOOPT: [[VSA:%.+]] = add <4 x i32> [[VSC2:%.+]], [[VSF]] int4 d = {1, 1, 1, 1}; int4 f = c + (d << 34); - //OPT-NEXT: ret <4 x i32> [[VSF]] + //NOOPT: ret <4 x i32> return f; } |