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| author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2015-04-29 16:22:46 +0000 |
|---|---|---|
| committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2015-04-29 16:22:46 +0000 |
| commit | cca29e8f6e75745a11ea65ac0b113c0a450d7481 (patch) | |
| tree | 33715cc665c088de35d69c3c3ddf52dc18f3daa6 | |
| parent | e5f4492e30cce5abb21755eebb3526f380197449 (diff) | |
| download | bcm5719-llvm-cca29e8f6e75745a11ea65ac0b113c0a450d7481.tar.gz bcm5719-llvm-cca29e8f6e75745a11ea65ac0b113c0a450d7481.zip | |
[mips][microMIPSr6] Implement SUB and SUBU instructions
Differential Revision: http://reviews.llvm.org/D8764
llvm-svn: 236118
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Mips/micromips32r6.txt | 5 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips32r6/valid.s | 3 |
3 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td index 9d6f0dfe306..a0f5dd84cdf 100644 --- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -24,6 +24,8 @@ class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>; class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>; class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>; class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>; +class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>; +class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>; //===----------------------------------------------------------------------===// // @@ -48,6 +50,8 @@ class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> { list<Register> Defs = [RA]; } class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>; +class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>; +class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>; class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> : MMR6Arch<instr_asm> { @@ -87,4 +91,6 @@ def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC, ISA_MICROMIPS32R6; def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6; def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6; +def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6; +def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6; } diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r6.txt b/llvm/test/MC/Disassembler/Mips/micromips32r6.txt index bb5fd9bf18a..36bbce2d820 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r6.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r6.txt @@ -20,3 +20,8 @@ # CHECK: pref 1, 8($5) 0x60 0x25 0x20 0x08 + +0x00 0xa4 0x19 0x90 # CHECK: sub $3, $4, $5 + +0x00 0xa4 0x19 0xd0 # CHECK: subu $3, $4, $5 + diff --git a/llvm/test/MC/Mips/micromips32r6/valid.s b/llvm/test/MC/Mips/micromips32r6/valid.s index 94d777af169..e1c2edfa132 100644 --- a/llvm/test/MC/Mips/micromips32r6/valid.s +++ b/llvm/test/MC/Mips/micromips32r6/valid.s @@ -9,3 +9,6 @@ bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x00,0x44,0x0b,0x3c] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x60,0x25,0x20,0x08] + sub $3, $4, $5 # CHECK: sub $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x90] + subu $3, $4, $5 # CHECK: subu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd0] + |
