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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-10 16:05:35 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-10 16:05:35 +0000 |
| commit | cbda7ff4aeda9791d153cbca80f3bd0f528657ba (patch) | |
| tree | 622b5645f6e56a7b9ed59853faa966c45f903b1d | |
| parent | e5606b4fa5b8b4e66ab7c01aa274a29580366a26 (diff) | |
| download | bcm5719-llvm-cbda7ff4aeda9791d153cbca80f3bd0f528657ba.tar.gz bcm5719-llvm-cbda7ff4aeda9791d153cbca80f3bd0f528657ba.zip | |
AMDGPU: Fix crash when constant folding with physreg operand
llvm-svn: 327209
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir | 27 |
2 files changed, 29 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp index ac3c7eb541a..67f64894270 100644 --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -471,7 +471,8 @@ static MachineOperand *getImmOrMaterializedImm(MachineRegisterInfo &MRI, MachineOperand &Op) { if (Op.isReg()) { // If this has a subregister, it obviously is a register source. - if (Op.getSubReg() != AMDGPU::NoSubRegister) + if (Op.getSubReg() != AMDGPU::NoSubRegister || + !TargetRegisterInfo::isVirtualRegister(Op.getReg())) return &Op; MachineInstr *Def = MRI.getVRegDef(Op.getReg()); diff --git a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir index e8e794f369a..11d7612d6d1 100644 --- a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir +++ b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir @@ -804,3 +804,30 @@ body: | S_ENDPGM ... +--- +# Make sure there is no crash if one of the operands is a physical register +# GCN-LABEL: name: constant_fold_physreg_op{{$}} +# GCN: %3:sreg_64 = S_AND_B64 $exec, 0, implicit-def dead $scc + +name: constant_fold_physreg_op +tracksRegLiveness: true +body: | + bb.0: + successors: %bb.1, %bb.3 + liveins: $vgpr0, $sgpr4_sgpr5 + + %19:sreg_64 = IMPLICIT_DEF + %0:sreg_64 = SI_IF killed %19, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec + S_BRANCH %bb.1 + + bb.1: + %6:sreg_64 = S_MOV_B64 0 + %7:sreg_64 = S_AND_B64 $exec, killed %6, implicit-def dead $scc + $vcc = COPY %7 + + bb.3: + liveins: $vcc + SI_END_CF %0, implicit-def dead $exec, implicit-def dead $scc, implicit $exec + S_ENDPGM implicit $vcc + +... |
