Let dwarf writer allocate extra space in the debug location expression. This space, if requested, will be used for complex addresses of the Blocks' variables.

llvm-svn: 130178

4 files changed, 14 insertions, 9 deletions

diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h b/llvm/include/llvm/CodeGen/AsmPrinter.h
index 1dac67119a5..56e125e0a95 100644
--- a/llvm/include/llvm/CodeGen/AsmPrinter.h
+++ b/llvm/include/llvm/CodeGen/AsmPrinter.h
@@ -384,7 +384,8 @@ namespace llvm {
     virtual unsigned getISAEncoding() { return 0; }
 
     /// EmitDwarfRegOp - Emit dwarf register operation.
-    virtual void EmitDwarfRegOp(const MachineLocation &MLoc) const;
+    virtual void EmitDwarfRegOp(const MachineLocation &MLoc,
+                                unsigned ExtraExprSize = 0) const;
 
     //===------------------------------------------------------------------===//
     // Dwarf Lowering Routines
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 609da254fce..a841ed6d60c 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -753,7 +753,8 @@ getDebugValueLocation(const MachineInstr *MI) const {
 }
 
 /// EmitDwarfRegOp - Emit dwarf register operation.
-void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
+void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
+                                unsigned ExtraExprSize) const {
   const TargetRegisterInfo *RI = TM.getRegisterInfo();
   unsigned Reg = RI->getDwarfRegNum(MLoc.getReg(), false);
   if (int Offset =  MLoc.getOffset()) {
@@ -761,7 +762,7 @@ void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
     // use DW_OP_fbreg.
     unsigned OffsetSize = Offset ? MCAsmInfo::getSLEB128Size(Offset) : 1;
     OutStreamer.AddComment("Loc expr size");
-    EmitInt16(1 + OffsetSize);
+    EmitInt16(1 + OffsetSize + ExtraExprSize);
     OutStreamer.AddComment(
       dwarf::OperationEncodingString(dwarf::DW_OP_fbreg));
     EmitInt8(dwarf::DW_OP_fbreg);
@@ -776,7 +777,7 @@ void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
       EmitInt8(dwarf::DW_OP_reg0 + Reg);
     } else {
       OutStreamer.AddComment("Loc expr size");
-      EmitInt16(1 + MCAsmInfo::getULEB128Size(Reg));
+      EmitInt16(1 + MCAsmInfo::getULEB128Size(Reg) + ExtraExprSize);
       OutStreamer.AddComment(
         dwarf::OperationEncodingString(dwarf::DW_OP_regx));
       EmitInt8(dwarf::DW_OP_regx);
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index b8c117c2cbe..10cccda5e8b 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -173,10 +173,11 @@ getDebugValueLocation(const MachineInstr *MI) const {
 }
 
 /// EmitDwarfRegOp - Emit dwarf register operation.
-void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
+void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
+                                   unsigned ExtraExprSize) const {
   const TargetRegisterInfo *RI = TM.getRegisterInfo();
   if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
-    AsmPrinter::EmitDwarfRegOp(MLoc);
+    AsmPrinter::EmitDwarfRegOp(MLoc, ExtraExprSize);
   else {
     unsigned Reg = MLoc.getReg();
     if (Reg >= ARM::S0 && Reg <= ARM::S31) {
@@ -191,7 +192,7 @@ void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
       OutStreamer.AddComment("Loc expr size");
       // DW_OP_regx + ULEB + DW_OP_bit_piece + ULEB + ULEB
       //   1 + ULEB(Rx) + 1 + 1 + 1
-      EmitInt16(4 + MCAsmInfo::getULEB128Size(Rx));
+      EmitInt16(4 + MCAsmInfo::getULEB128Size(Rx) + ExtraExprSize);
 
       OutStreamer.AddComment("DW_OP_regx for S register");
       EmitInt8(dwarf::DW_OP_regx);
@@ -223,7 +224,8 @@ void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
       // DW_OP_regx + ULEB + DW_OP_piece + ULEB(8) +
       // DW_OP_regx + ULEB + DW_OP_piece + ULEB(8);
       //   6 + ULEB(D1) + ULEB(D2)
-      EmitInt16(6 + MCAsmInfo::getULEB128Size(D1) + MCAsmInfo::getULEB128Size(D2));
+      EmitInt16(6 + MCAsmInfo::getULEB128Size(D1) 
+                + MCAsmInfo::getULEB128Size(D2) + ExtraExprSize);
 
       OutStreamer.AddComment("DW_OP_regx for Q register: D1");
       EmitInt8(dwarf::DW_OP_regx);
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.h b/llvm/lib/Target/ARM/ARMAsmPrinter.h
index 5f9169ef7f7..e94901449a1 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.h
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.h
@@ -90,7 +90,8 @@ public:
   MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
 
   /// EmitDwarfRegOp - Emit dwarf register operation.
-  virtual void EmitDwarfRegOp(const MachineLocation &MLoc) const;
+  virtual void EmitDwarfRegOp(const MachineLocation &MLoc,
+                              unsigned ExtraExprSize = 0) const;
 
   virtual unsigned getISAEncoding() {
     // ARM/Darwin adds ISA to the DWARF info for each function.