[mips] Remove single-precision floating point instruction from multiclass

FFR2P_M.
 

llvm-svn: 170055

2 files changed, 13 insertions, 10 deletions

diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td
index 389f154837b..efdbc6e88ba 100644
--- a/llvm/lib/Target/Mips/MipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MipsInstrFPU.td
@@ -139,10 +139,9 @@ multiclass FFR1P_M<bits<6> funct, string opstr, SDNode OpNode> {
 
 multiclass FFR2P_M<bits<6> funct, string opstr, SDNode OpNode, bit isComm = 0> {
   let isCommutable = isComm in {
-  def _S   : FFR2P<funct, 16, opstr, "s", FGR32, OpNode>;
-  def _D32 : FFR2P<funct, 17, opstr, "d", AFGR64, OpNode>,
+  def _D32 : FFR2P<funct, 17, opstr, AFGR64, OpNode>,
              Requires<[NotFP64bit, HasStdEnc]>;
-  def _D64 : FFR2P<funct, 17, opstr, "d", FGR64, OpNode>,
+  def _D64 : FFR2P<funct, 17, opstr, FGR64, OpNode>,
              Requires<[IsFP64bit, HasStdEnc]> {
     let DecoderNamespace = "Mips64";
   }
@@ -325,10 +324,14 @@ let Predicates = [HasMips64, HasStdEnc],
 }
 
 /// Floating-point Aritmetic
-defm FADD : FFR2P_M<0x00, "add", fadd, 1>;
-defm FDIV : FFR2P_M<0x03, "div", fdiv>;
-defm FMUL : FFR2P_M<0x02, "mul", fmul, 1>;
-defm FSUB : FFR2P_M<0x01, "sub", fsub>;
+def FADD_S : FFR2P<0x00, 16, "add.s", FGR32, fadd>, IsCommutable;
+defm FADD : FFR2P_M<0x00, "add.d", fadd, 1>;
+def FDIV_S : FFR2P<0x03, 16, "div.s", FGR32, fdiv>;
+defm FDIV : FFR2P_M<0x03, "div.d", fdiv>;
+def FMUL_S : FFR2P<0x02, 16, "mul.s", FGR32, fmul>, IsCommutable;
+defm FMUL : FFR2P_M<0x02, "mul.d", fmul, 1>;
+def FSUB_S : FFR2P<0x01, 16, "sub.s", FGR32, fsub>;
+defm FSUB : FFR2P_M<0x01, "sub.d", fsub>;
 
 let Predicates = [HasMips32r2, HasStdEnc] in {
   def MADD_S : FMADDSUB<0x4, 0, "madd", "s", fadd, FGR32>;
diff --git a/llvm/lib/Target/Mips/MipsInstrFormats.td b/llvm/lib/Target/Mips/MipsInstrFormats.td
index 5c20a1e5867..e081fd5ab1e 100644
--- a/llvm/lib/Target/Mips/MipsInstrFormats.td
+++ b/llvm/lib/Target/Mips/MipsInstrFormats.td
@@ -333,10 +333,10 @@ class FFR1P<bits<6> funct, bits<5> fmt, string opstr, RegisterClass DstRC,
   let ft = 0;
 }
 
-class FFR2P<bits<6> funct, bits<5> fmt, string opstr,
-            string fmtstr, RegisterClass RC, SDNode OpNode> :
+class FFR2P<bits<6> funct, bits<5> fmt, string opstr, RegisterClass RC,
+            SDNode OpNode> :
   FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft),
-      !strconcat(opstr, ".", fmtstr, "\t$fd, $fs, $ft"),
+      !strconcat(opstr, "\t$fd, $fs, $ft"),
       [(set RC:$fd, (OpNode RC:$fs, RC:$ft))]>;
 
 // Floating point madd/msub/nmadd/nmsub.