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| author | Silviu Baranga <silviu.baranga@arm.com> | 2012-04-18 14:18:57 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2012-04-18 14:18:57 +0000 |
| commit | ca45af9a755c454cbaa131b3823b9cab118c1fe5 (patch) | |
| tree | cfba8e7a5ad093359aff7fdff30291b59a621594 | |
| parent | d5c6a63a500f903c1e2430e27a3ed9fbb62f935a (diff) | |
| download | bcm5719-llvm-ca45af9a755c454cbaa131b3823b9cab118c1fe5.tar.gz bcm5719-llvm-ca45af9a755c454cbaa131b3823b9cab118c1fe5.zip | |
Added support for disassembling unpredictable swp/swpb ARM instructions.
llvm-svn: 155004
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrFormats.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt | 26 |
4 files changed, 33 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td index 1d38bcf9e84..f04926aaceb 100644 --- a/llvm/lib/Target/ARM/ARMInstrFormats.td +++ b/llvm/lib/Target/ARM/ARMInstrFormats.td @@ -532,6 +532,7 @@ class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> let Inst{11-4} = 0b00001001; let Inst{3-0} = Rt2; + let Unpredictable{11-8} = 0b1111; let DecoderMethod = "DecodeSwap"; } diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 807577e7696..1eb561d6901 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -4280,9 +4280,9 @@ def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>, // SWP/SWPB are deprecated in V6/V7. let mayLoad = 1, mayStore = 1 in { -def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr), +def SWP : AIswp<0, (outs GPRnopc:$Rt), (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>; -def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr), +def SWPB: AIswp<1, (outs GPRnopc:$Rt), (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>; } diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 87a5f019d4a..912935db17a 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -4310,6 +4310,10 @@ static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, return DecodeCPSInstruction(Inst, Insn, Address, Decoder); DecodeStatus S = MCDisassembler::Success; + + if (Rt == Rn || Rn == Rt2) + S = MCDisassembler::SoftFail; + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) diff --git a/llvm/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt b/llvm/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt new file mode 100644 index 00000000000..64bb171bf81 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt @@ -0,0 +1,26 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x9f 0x10 0x03 0x01 +0x9f 0x10 0x03 0x01 + +# CHECK: potentially undefined +# CHECK: 0x90 0xf0 0x03 0x01 +0x90 0xf0 0x03 0x01 + +# CHECK: potentially undefined +# CHECK: 0x90 0x1f 0x03 0x01 +0x90 0x1f 0x03 0x01 + +# CHECK: potentially undefined +# CHECK: 0x90 0x10 0x0f 0x01 +0x90 0x10 0x0f 0x01 + +# CHECK: potentially undefined +# CHECK: 0x90 0x10 0x01 0x01 +0x90 0x10 0x01 0x01 + +# CHECK: potentially undefined +# CHECK: 0x90 0x10 0x00 0x01 +0x90 0x10 0x00 0x01 + |
