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author | Craig Topper <craig.topper@gmail.com> | 2012-11-15 08:02:19 +0000 |
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committer | Craig Topper <craig.topper@gmail.com> | 2012-11-15 08:02:19 +0000 |
commit | c8a2adf1ca44ce3c54f09170f8027059a6deff14 (patch) | |
tree | dee7baf57481a8893f8554881fdb1b6dba178651 | |
parent | 65992f454c994d126e57704e74ffb1b7a01914d9 (diff) | |
download | bcm5719-llvm-c8a2adf1ca44ce3c54f09170f8027059a6deff14.tar.gz bcm5719-llvm-c8a2adf1ca44ce3c54f09170f8027059a6deff14.zip |
Make a bunch of floating point operations on vectors Expand so that instruction selection won't fail.
llvm-svn: 168028
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index f7a7cfa890c..d51baa6a576 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -347,6 +347,16 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) setOperationAction(ISD::UREM, VT, Expand); setOperationAction(ISD::FDIV, VT, Expand); setOperationAction(ISD::FNEG, VT, Expand); + setOperationAction(ISD::FSQRT, VT, Expand); + setOperationAction(ISD::FLOG, VT, Expand); + setOperationAction(ISD::FLOG10, VT, Expand); + setOperationAction(ISD::FLOG2, VT, Expand); + setOperationAction(ISD::FEXP, VT, Expand); + setOperationAction(ISD::FEXP2, VT, Expand); + setOperationAction(ISD::FSIN, VT, Expand); + setOperationAction(ISD::FCOS, VT, Expand); + setOperationAction(ISD::FABS, VT, Expand); + setOperationAction(ISD::FPOWI, VT, Expand); setOperationAction(ISD::FFLOOR, VT, Expand); setOperationAction(ISD::FCEIL, VT, Expand); setOperationAction(ISD::FTRUNC, VT, Expand); @@ -378,12 +388,6 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) setLoadExtAction(ISD::EXTLOAD, VT, Expand); } - for (unsigned i = (unsigned)MVT::FIRST_FP_VECTOR_VALUETYPE; - i <= (unsigned)MVT::LAST_FP_VECTOR_VALUETYPE; ++i) { - MVT::SimpleValueType VT = (MVT::SimpleValueType)i; - setOperationAction(ISD::FSQRT, VT, Expand); - } - // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle // with merges, splats, etc. setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); |