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| author | Chris Lattner <sabre@nondot.org> | 2008-10-17 17:59:52 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2008-10-17 17:59:52 +0000 |
| commit | c7e65f4377f383df28b6b4318354b7285e3039fd (patch) | |
| tree | 012d9874515be2fd3fd27780747cfebeb8457687 | |
| parent | 052092bf9c1a1a32a7a59a7e91467427985fb922 (diff) | |
| download | bcm5719-llvm-c7e65f4377f383df28b6b4318354b7285e3039fd.tar.gz bcm5719-llvm-c7e65f4377f383df28b6b4318354b7285e3039fd.zip | |
Fix a bug where the x86 backend would reject 64-bit r constraints when
in 32-bit mode instead of assigning a register pair. This has nothing to
do with PR2356, but I happened to notice it while working on it.
llvm-svn: 57704
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll | 9 |
2 files changed, 10 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index d32a9f052d4..0607797b713 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -7511,7 +7511,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, case 'l': // INDEX_REGS if (VT == MVT::i64 && Subtarget->is64Bit()) return std::make_pair(0U, X86::GR64RegisterClass); - if (VT == MVT::i32) + if (VT == MVT::i32 || VT == MVT::i64) return std::make_pair(0U, X86::GR32RegisterClass); else if (VT == MVT::i16) return std::make_pair(0U, X86::GR16RegisterClass); diff --git a/llvm/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll b/llvm/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll new file mode 100644 index 00000000000..eb2ec3760b9 --- /dev/null +++ b/llvm/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=x86 +; RUN: llvm-as < %s | llc -march=x86-64 + +define void @test(i64 %x) nounwind { +entry: + tail call void asm sideeffect "ASM: $0", "r,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind + ret void +} + |
