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| author | Joey Gouly <joey.gouly@arm.com> | 2013-08-23 15:20:56 +0000 |
|---|---|---|
| committer | Joey Gouly <joey.gouly@arm.com> | 2013-08-23 15:20:56 +0000 |
| commit | c7cda1c59ef9559331160cd6d48d8f7e6177a180 (patch) | |
| tree | 9a53923085822d8e7ff138b83a94924a3faf6ee6 | |
| parent | 0649d361722b9a2e74b0cea1e9c0594028949fb7 (diff) | |
| download | bcm5719-llvm-c7cda1c59ef9559331160cd6d48d8f7e6177a180.tar.gz bcm5719-llvm-c7cda1c59ef9559331160cd6d48d8f7e6177a180.zip | |
[ARM] Fix another ARM FastISel -verify-machineinstrs issue.
llvm-svn: 189109
| -rw-r--r-- | llvm/lib/Target/ARM/ARMFastISel.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/fast-isel-binary.ll | 6 |
2 files changed, 7 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp index 628b5141408..0927e9a8cc0 100644 --- a/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -1182,6 +1182,7 @@ bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr, (const TargetRegisterClass*)&ARM::tGPRRegClass : (const TargetRegisterClass*)&ARM::GPRRegClass); unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri; + SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), Res) .addReg(SrcReg).addImm(1)); @@ -1253,6 +1254,7 @@ bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr, ARMSimplifyAddress(Addr, VT, useAM3); // Create the base instruction, then add the operands. + SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0); MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(StrOpc)) .addReg(SrcReg); @@ -1856,6 +1858,8 @@ bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) { if (SrcReg2 == 0) return false; unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); + SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1); + SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) .addReg(SrcReg1).addReg(SrcReg2)); diff --git a/llvm/test/CodeGen/ARM/fast-isel-binary.ll b/llvm/test/CodeGen/ARM/fast-isel-binary.ll index 31596276f37..e1a2a4f3383 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-binary.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-binary.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; Test add with non-legal types |
