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| author | Jim Grosbach <grosbach@apple.com> | 2012-03-05 21:09:58 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2012-03-05 21:09:58 +0000 |
| commit | c71bf4739a212d2cc07f380915f5d6d210523059 (patch) | |
| tree | 7e0d091e1d6a8ddc5df67513df9ea7c726ecf08c | |
| parent | e5617c79e4e13ce1fb9d408aec299e03db11b3e5 (diff) | |
| download | bcm5719-llvm-c71bf4739a212d2cc07f380915f5d6d210523059.tar.gz bcm5719-llvm-c71bf4739a212d2cc07f380915f5d6d210523059.zip | |
ARM Remove a bit of dead code.
llvm-svn: 152061
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrNEON.td | 9 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 5 |
2 files changed, 0 insertions, 14 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index b0ab9941f96..1fa3979b3d3 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -89,15 +89,6 @@ def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> { let ParserMatchClass = VecListOneDAsmOperand; } // Register list of two sequential D registers. -def VecListTwoDAsmOperand : AsmOperandClass { - let Name = "VecListTwoD"; - let ParserMethod = "parseVectorList"; - let RenderMethod = "addVecListOperands"; -} -def VecListTwoD : RegisterOperand<DPR, "printVectorListTwo"> { - let ParserMatchClass = VecListTwoDAsmOperand; -} -// FIXME: Replace all VecListTwoD with VecListDPair def VecListDPairAsmOperand : AsmOperandClass { let Name = "VecListDPair"; let ParserMethod = "parseVectorList"; diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 845f0a32996..b3e7e45b8c0 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -1085,11 +1085,6 @@ public: return VectorList.Count == 1; } - bool isVecListTwoD() const { - if (!isSingleSpacedVectorList()) return false; - return VectorList.Count == 2; - } - bool isVecListDPair() const { if (!isSingleSpacedVectorList()) return false; return (ARMMCRegisterClasses[ARM::DPairRegClassID] |
