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| author | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2017-12-22 17:13:28 +0000 |
|---|---|---|
| committer | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2017-12-22 17:13:28 +0000 |
| commit | c5b0c172f65591901367413a20909d3ce96b8f2b (patch) | |
| tree | f4831e00a242d48a5efc7a21b8c3110beaf82cb3 | |
| parent | 6d14dfe8f3766142e05da2e96e030b70f97e6a85 (diff) | |
| download | bcm5719-llvm-c5b0c172f65591901367413a20909d3ce96b8f2b.tar.gz bcm5719-llvm-c5b0c172f65591901367413a20909d3ce96b8f2b.zip | |
[AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32
See bug 35645: https://bugs.llvm.org/show_bug.cgi?id=35645
Reviewers: artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D41186
llvm-svn: 321367
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/MC/AMDGPU/ds.s | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AMDGPU/ds_vi.txt | 3 |
3 files changed, 10 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 7ecaf0bf87c..25a4420a331 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -3852,7 +3852,9 @@ AMDGPUAsmParser::parseSwizzleOp(OperandVector &Operands) { return Ok? MatchOperand_Success : MatchOperand_ParseFail; } else { - return MatchOperand_NoMatch; + // Swizzle "offset" operand is optional. + // If it is omitted, try parsing other optional operands. + return parseOptionalOperand(Operands); } } diff --git a/llvm/test/MC/AMDGPU/ds.s b/llvm/test/MC/AMDGPU/ds.s index ef36a98f746..b06101a4051 100644 --- a/llvm/test/MC/AMDGPU/ds.s +++ b/llvm/test/MC/AMDGPU/ds.s @@ -511,6 +511,10 @@ ds_swizzle_b32 v8, v2 // SICI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08] // VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08] +ds_swizzle_b32 v8, v2 gds +// SICI: ds_swizzle_b32 v8, v2 gds ; encoding: [0x00,0x00,0xd6,0xd8,0x02,0x00,0x00,0x08] +// VI: ds_swizzle_b32 v8, v2 gds ; encoding: [0x00,0x00,0x7b,0xd8,0x02,0x00,0x00,0x08] + ds_swizzle_b32 v8, v2 offset:0xFFFF // SICI: ds_swizzle_b32 v8, v2 offset:65535 ; encoding: [0xff,0xff,0xd4,0xd8,0x02,0x00,0x00,0x08] // VI: ds_swizzle_b32 v8, v2 offset:65535 ; encoding: [0xff,0xff,0x7a,0xd8,0x02,0x00,0x00,0x08] diff --git a/llvm/test/MC/Disassembler/AMDGPU/ds_vi.txt b/llvm/test/MC/Disassembler/AMDGPU/ds_vi.txt index 6d910ea5bb5..c12e7a157e8 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/ds_vi.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/ds_vi.txt @@ -171,6 +171,9 @@ # VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08] 0x00 0x00 0x7a 0xd8 0x02 0x00 0x00 0x08 +# VI: ds_swizzle_b32 v8, v2 gds ; encoding: [0x00,0x00,0x7b,0xd8,0x02,0x00,0x00,0x08] +0x00 0x00 0x7b 0xd8 0x02 0x00 0x00 0x08 + # VI: ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0x6c,0xd8,0x02,0x00,0x00,0x08] 0x00 0x00 0x6c 0xd8 0x02 0x00 0x00 0x08 |
