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authorSimon Dardis <simon.dardis@imgtec.com>2016-10-18 14:42:13 +0000
committerSimon Dardis <simon.dardis@imgtec.com>2016-10-18 14:42:13 +0000
commitc4463c942c0914bc7c9f0bef16b14aef142cedad (patch)
tree64058c1a00163f205907a98a4b8711575f3fbf5f
parent197aa3192dd8d25330c23274a0d257c6130e4e09 (diff)
downloadbcm5719-llvm-c4463c942c0914bc7c9f0bef16b14aef142cedad.tar.gz
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[mips] Fix sync instruction definition
The 'sync' instruction for MIPS was defined in MIPS-II as taking no operands. MIPS32 extended the define of 'sync' as taking an optional unsigned 5 bit immediate. This patch correct the definition of sync so that it is accepted with an operand of 0 or no operand for MIPS-II to MIPS-V, and a 5 bit unsigned immediate for MIPS32 and later revisions. Additionally a clear error is given when the MIPS32 version of sync is used when targeting pre MIPS32. This partially resolves PR/30714. Thanks to Daniel Sanders for reporting this issue! Reveiwers: vkalintiris Differential Revision: https://reviews.llvm.org/D25672 llvm-svn: 284483
Diffstat
-rw-r--r--llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp7
-rw-r--r--llvm/lib/Target/Mips/MipsInstrInfo.td3
-rw-r--r--llvm/test/MC/Mips/mips2/invalid-mips32.s3
-rw-r--r--llvm/test/MC/Mips/mips2/valid.s1
-rw-r--r--llvm/test/MC/Mips/mips3/invalid-mips32.s3
-rw-r--r--llvm/test/MC/Mips/mips3/valid.s1
-rw-r--r--llvm/test/MC/Mips/mips4/invalid-mips32.s3
-rw-r--r--llvm/test/MC/Mips/mips4/valid.s1
-rw-r--r--llvm/test/MC/Mips/mips5/invalid-mips32.s3
-rw-r--r--llvm/test/MC/Mips/mips5/valid.s1
10 files changed, 16 insertions, 10 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index d0fe076c4b4..ec8873289d6 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -404,6 +404,7 @@ public:
Match_RequiresDifferentOperands,
Match_RequiresNoZeroRegister,
Match_RequiresSameSrcAndDst,
+ Match_NonZeroOperandForSync,
#define GET_OPERAND_DIAGNOSTIC_TYPES
#include "MipsGenAsmMatcher.inc"
#undef GET_OPERAND_DIAGNOSTIC_TYPES
@@ -3955,6 +3956,10 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
if (Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg())
return Match_RequiresDifferentSrcAndDst;
return Match_Success;
+ case Mips::SYNC:
+ if (Inst.getOperand(0).getImm() != 0 && !hasMips32())
+ return Match_NonZeroOperandForSync;
+ return Match_Success;
// As described the MIPSR6 spec, the compact branches that compare registers
// must:
// a) Not use the zero register.
@@ -4052,6 +4057,8 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return Error(ErrorLoc, "invalid operand for instruction");
}
+ case Match_NonZeroOperandForSync:
+ return Error(IDLoc, "s-type must be zero or unspecified for pre-MIPS32 ISAs");
case Match_MnemonicFail:
return Error(IDLoc, "invalid instruction");
case Match_RequiresDifferentSrcAndDst:
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index 2900a3f4e66..ea4a8e68b71 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -1876,8 +1876,7 @@ let DecoderNamespace = "COP3_" in {
}
}
-def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM,
- ISA_MIPS32;
+def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS2;
def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
let AdditionalPredicates = [NotInMicroMips] in {
diff --git a/llvm/test/MC/Mips/mips2/invalid-mips32.s b/llvm/test/MC/Mips/mips2/invalid-mips32.s
index 43ea345441c..1e451fd2466 100644
--- a/llvm/test/MC/Mips/mips2/invalid-mips32.s
+++ b/llvm/test/MC/Mips/mips2/invalid-mips32.s
@@ -40,5 +40,4 @@
msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: s-type must be zero or unspecified for pre-MIPS32 ISAs
diff --git a/llvm/test/MC/Mips/mips2/valid.s b/llvm/test/MC/Mips/mips2/valid.s
index 16dccd36f12..3a5fd1cb28f 100644
--- a/llvm/test/MC/Mips/mips2/valid.s
+++ b/llvm/test/MC/Mips/mips2/valid.s
@@ -159,6 +159,7 @@ a:
swl $15,13694($s3)
swr $s1,-26590($14)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
+ sync 0 # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
diff --git a/llvm/test/MC/Mips/mips3/invalid-mips32.s b/llvm/test/MC/Mips/mips3/invalid-mips32.s
index 3acd7651e62..bedbb00d0e7 100644
--- a/llvm/test/MC/Mips/mips3/invalid-mips32.s
+++ b/llvm/test/MC/Mips/mips3/invalid-mips32.s
@@ -6,5 +6,4 @@
.set noat
- sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: s-type must be zero or unspecified for pre-MIPS32 ISAs
diff --git a/llvm/test/MC/Mips/mips3/valid.s b/llvm/test/MC/Mips/mips3/valid.s
index 8f0e29db415..69244e35d2b 100644
--- a/llvm/test/MC/Mips/mips3/valid.s
+++ b/llvm/test/MC/Mips/mips3/valid.s
@@ -223,6 +223,7 @@ a:
swl $15,13694($s3)
swr $s1,-26590($14)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
+ sync 0 # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
diff --git a/llvm/test/MC/Mips/mips4/invalid-mips32.s b/llvm/test/MC/Mips/mips4/invalid-mips32.s
index 52dea02d10c..6d7366dcc31 100644
--- a/llvm/test/MC/Mips/mips4/invalid-mips32.s
+++ b/llvm/test/MC/Mips/mips4/invalid-mips32.s
@@ -6,5 +6,4 @@
.set noat
- sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: s-type must be zero or unspecified for pre-MIPS32 ISAs
diff --git a/llvm/test/MC/Mips/mips4/valid.s b/llvm/test/MC/Mips/mips4/valid.s
index e9a7ae90dd5..c8fb99bd9de 100644
--- a/llvm/test/MC/Mips/mips4/valid.s
+++ b/llvm/test/MC/Mips/mips4/valid.s
@@ -256,6 +256,7 @@ a:
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
+ sync 0 # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
diff --git a/llvm/test/MC/Mips/mips5/invalid-mips32.s b/llvm/test/MC/Mips/mips5/invalid-mips32.s
index 2e2c8da462d..3911eebebdc 100644
--- a/llvm/test/MC/Mips/mips5/invalid-mips32.s
+++ b/llvm/test/MC/Mips/mips5/invalid-mips32.s
@@ -6,5 +6,4 @@
.set noat
- sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: s-type must be zero or unspecified for pre-MIPS32 ISAs
diff --git a/llvm/test/MC/Mips/mips5/valid.s b/llvm/test/MC/Mips/mips5/valid.s
index 62b1b48c767..50f318dee00 100644
--- a/llvm/test/MC/Mips/mips5/valid.s
+++ b/llvm/test/MC/Mips/mips5/valid.s
@@ -258,6 +258,7 @@ a:
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
+ sync 0 # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
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