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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2017-09-11 11:11:17 +0000 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2017-09-11 11:11:17 +0000 |
| commit | c429aabb916fbf951abcb1c091239db642ccb233 (patch) | |
| tree | 140cf4cd82e0060d28ad05b2c3cd36aa0dee8073 | |
| parent | 9707ba09570740288416dd187eece06375ac79c3 (diff) | |
| download | bcm5719-llvm-c429aabb916fbf951abcb1c091239db642ccb233.tar.gz bcm5719-llvm-c429aabb916fbf951abcb1c091239db642ccb233.zip | |
[ARM] Enable the use of SVC anywhere in an IT block
Differential Revision: https://reviews.llvm.org/D37374
llvm-svn: 312908
| -rw-r--r-- | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/basic-thumb2-instructions.s | 6 |
2 files changed, 10 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 5e5931dcf21..43135ad2103 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -8717,9 +8717,10 @@ template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) { bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const { const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); - // All branch & call instructions terminate IT blocks. - if (MCID.isTerminator() || MCID.isCall() || MCID.isReturn() || - MCID.isBranch() || MCID.isIndirectBranch()) + // All branch & call instructions terminate IT blocks with the exception of + // SVC. + if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) || + MCID.isReturn() || MCID.isBranch() || MCID.isIndirectBranch()) return true; // Any arithmetic instruction which writes to the PC also terminates the IT diff --git a/llvm/test/MC/ARM/basic-thumb2-instructions.s b/llvm/test/MC/ARM/basic-thumb2-instructions.s index b1cb53cdace..6f81f00350d 100644 --- a/llvm/test/MC/ARM/basic-thumb2-instructions.s +++ b/llvm/test/MC/ARM/basic-thumb2-instructions.s @@ -3113,12 +3113,18 @@ _func: svceq #255 it ne swine #33 + itt eq + svceq #0 + svceq #1 @ CHECK: svc #0 @ encoding: [0x00,0xdf] @ CHECK: it eq @ encoding: [0x08,0xbf] @ CHECK: svceq #255 @ encoding: [0xff,0xdf] @ CHECK: it ne @ encoding: [0x18,0xbf] @ CHECK: svcne #33 @ encoding: [0x21,0xdf] +@ CHECK: itt eq @ encoding: [0x04,0xbf] +@ CHECK: svceq #0 @ encoding: [0x00,0xdf] +@ CHECK: svceq #1 @ encoding: [0x01,0xdf] @------------------------------------------------------------------------------ |
