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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-03-03 14:37:57 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-03-03 14:37:57 +0000 |
| commit | c37a32d2b907d0f43ca0a72d92ef9ae1b672f669 (patch) | |
| tree | 6c0a33eadd9f3788a1bc87319c8f5c04897ab568 | |
| parent | 03880f8d247052c6efdf16d3808d294dc726af33 (diff) | |
| download | bcm5719-llvm-c37a32d2b907d0f43ca0a72d92ef9ae1b672f669.tar.gz bcm5719-llvm-c37a32d2b907d0f43ca0a72d92ef9ae1b672f669.zip | |
Use APInt::getHighBitsSet instead of APInt::getBitsSet for upper bit mask creation
llvm-svn: 296874
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 65d5ad3f242..4770327a69d 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -7498,7 +7498,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { // a constant pool load than it is to do a movd + shuffle. if (ExtVT == MVT::i64 && !Subtarget.is64Bit() && (!IsAllConstants || Idx == 0)) { - if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { + if (DAG.MaskedValueIsZero(Item, APInt::getHighBitsSet(64, 32))) { // Handle SSE only. assert(VT == MVT::v2i64 && "Expected an SSE value type!"); MVT VecVT = MVT::v4i32; |
