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authorPetar Jovanovic <petar.jovanovic@imgtec.com>2014-09-26 14:16:06 +0000
committerPetar Jovanovic <petar.jovanovic@imgtec.com>2014-09-26 14:16:06 +0000
commitc2e0427b940c84195b65e96e8de35bc4e37353e8 (patch)
treeef05bf33613e9d05cc14bf40a1f544e8d8a11a00
parent4dcb6aded223d2810e35b237baaeafb11c7ee185 (diff)
downloadbcm5719-llvm-c2e0427b940c84195b65e96e8de35bc4e37353e8.tar.gz
bcm5719-llvm-c2e0427b940c84195b65e96e8de35bc4e37353e8.zip
[UBSan] Adding support of MIPS32
Changed files: config-ix.cmake: Enabled UBSan for MIPS32 sanitizer_stacktrace.cc: Program counter for MIPS32 is four byte aligned and a delay slot so subtracted PC by 8 for getting call site address. cast-overflow.cpp: Added big endian support for this test case. Patch by Sagar Thakur. Differential Revision: http://reviews.llvm.org/D4881 llvm-svn: 218519
-rw-r--r--compiler-rt/cmake/config-ix.cmake2
-rw-r--r--compiler-rt/lib/sanitizer_common/sanitizer_stacktrace.cc2
-rw-r--r--compiler-rt/test/ubsan/TestCases/Float/cast-overflow.cpp9
3 files changed, 11 insertions, 2 deletions
diff --git a/compiler-rt/cmake/config-ix.cmake b/compiler-rt/cmake/config-ix.cmake
index 8035f7eb531..44f85c6592e 100644
--- a/compiler-rt/cmake/config-ix.cmake
+++ b/compiler-rt/cmake/config-ix.cmake
@@ -134,7 +134,7 @@ filter_available_targets(LSAN_COMMON_SUPPORTED_ARCH
filter_available_targets(MSAN_SUPPORTED_ARCH x86_64)
filter_available_targets(PROFILE_SUPPORTED_ARCH x86_64 i386 arm aarch64)
filter_available_targets(TSAN_SUPPORTED_ARCH x86_64)
-filter_available_targets(UBSAN_SUPPORTED_ARCH x86_64 i386 arm aarch64)
+filter_available_targets(UBSAN_SUPPORTED_ARCH x86_64 i386 arm aarch64 mips)
if(ANDROID)
set(OS_NAME "Android")
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace.cc b/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace.cc
index 21f710ddd83..7a00e3ad8f7 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace.cc
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace.cc
@@ -25,7 +25,7 @@ uptr StackTrace::GetPreviousInstructionPc(uptr pc) {
#if defined(__powerpc__) || defined(__powerpc64__)
// PCs are always 4 byte aligned.
return pc - 4;
-#elif defined(__sparc__)
+#elif defined(__sparc__) || defined(__mips__)
return pc - 8;
#else
return pc - 1;
diff --git a/compiler-rt/test/ubsan/TestCases/Float/cast-overflow.cpp b/compiler-rt/test/ubsan/TestCases/Float/cast-overflow.cpp
index 28a6672b0e0..b9d88d23c73 100644
--- a/compiler-rt/test/ubsan/TestCases/Float/cast-overflow.cpp
+++ b/compiler-rt/test/ubsan/TestCases/Float/cast-overflow.cpp
@@ -14,6 +14,7 @@
// This test assumes float and double are IEEE-754 single- and double-precision.
+#include <endian.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
@@ -41,12 +42,20 @@ int main(int argc, char **argv) {
unsigned Zero = NearlyMinusOne; // ok
// Build a '+Inf'.
+#if __BYTE_ORDER == __LITTLE_ENDIAN
char InfVal[] = { 0x00, 0x00, 0x80, 0x7f };
+#else
+ char InfVal[] = { 0x7f, 0x80, 0x00, 0x00 };
+#endif
float Inf;
memcpy(&Inf, InfVal, 4);
// Build a 'NaN'.
+#if __BYTE_ORDER == __LITTLE_ENDIAN
char NaNVal[] = { 0x01, 0x00, 0x80, 0x7f };
+#else
+ char NaNVal[] = { 0x7f, 0x80, 0x00, 0x01 };
+#endif
float NaN;
memcpy(&NaN, NaNVal, 4);
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