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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-21 19:27:33 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-21 19:27:33 +0000 |
| commit | c2a44e4c3c4cdcb5a68789ad53ca61c853150c79 (patch) | |
| tree | fe7f7fe08b6e14727dd8a61db8b11ef000c858a0 | |
| parent | e0bf7d02f037a5ba015dd468b483c17350b7d7b4 (diff) | |
| download | bcm5719-llvm-c2a44e4c3c4cdcb5a68789ad53ca61c853150c79.tar.gz bcm5719-llvm-c2a44e4c3c4cdcb5a68789ad53ca61c853150c79.zip | |
AMDGPU: Remove llvm.AMDGPU.flbit intrinsic
llvm-svn: 295754
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUIntrinsics.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll | 25 |
3 files changed, 0 insertions, 29 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIntrinsics.td b/llvm/lib/Target/AMDGPU/AMDGPUIntrinsics.td index d4263e2d878..a5724cdea6e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUIntrinsics.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUIntrinsics.td @@ -17,9 +17,6 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in { def int_AMDGPU_kill : Intrinsic<[], [llvm_float_ty], []>; def int_AMDGPU_kilp : Intrinsic<[], [], []>; - // Deprecated in favor of llvm.amdgcn.sffbh - def int_AMDGPU_flbit_i32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>; - // Deprecated in favor of expanded bit operations def int_AMDGPU_bfe_i32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_AMDGPU_bfe_u32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 7005c6a85c0..b0410b56cf3 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -2809,7 +2809,6 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, return DAG.getNode(AMDGPUISD::FMUL_LEGACY, DL, VT, Op.getOperand(1), Op.getOperand(2)); case Intrinsic::amdgcn_sffbh: - case AMDGPUIntrinsic::AMDGPU_flbit_i32: // Legacy name. return DAG.getNode(AMDGPUISD::FFBH_I32, DL, VT, Op.getOperand(1)); default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll index d453d03cded..09f8f485869 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll @@ -2,7 +2,6 @@ ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s declare i32 @llvm.amdgcn.sffbh.i32(i32) #1 -declare i32 @llvm.AMDGPU.flbit.i32(i32) #1 ; FUNC-LABEL: {{^}}s_flbit: ; GCN: s_load_dword [[VAL:s[0-9]+]], @@ -26,29 +25,5 @@ define void @v_flbit(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias % ret void } -; FUNC-LABEL: {{^}}legacy_s_flbit: -; GCN: s_load_dword [[VAL:s[0-9]+]], -; GCN: s_flbit_i32 [[SRESULT:s[0-9]+]], [[VAL]] -; GCN: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] -; GCN: buffer_store_dword [[VRESULT]], -; GCN: s_endpgm -define void @legacy_s_flbit(i32 addrspace(1)* noalias %out, i32 %val) nounwind { - %r = call i32 @llvm.AMDGPU.flbit.i32(i32 %val) nounwind readnone - store i32 %r, i32 addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}legacy_v_flbit: -; GCN: buffer_load_dword [[VAL:v[0-9]+]], -; GCN: v_ffbh_i32_e32 [[RESULT:v[0-9]+]], [[VAL]] -; GCN: buffer_store_dword [[RESULT]], -; GCN: s_endpgm -define void @legacy_v_flbit(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { - %val = load i32, i32 addrspace(1)* %valptr, align 4 - %r = call i32 @llvm.AMDGPU.flbit.i32(i32 %val) nounwind readnone - store i32 %r, i32 addrspace(1)* %out, align 4 - ret void -} - attributes #0 = { nounwind } attributes #1 = { nounwind readnone } |
