diff options
| author | Chad Rosier <mcrosier@codeaurora.org> | 2013-10-21 20:12:01 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@codeaurora.org> | 2013-10-21 20:12:01 +0000 |
| commit | c2a0b13c25c1a44053a2502384b38eaf1813aee1 (patch) | |
| tree | 8bf67b366df51cf3aca2bf013b3d3f41d80920e7 | |
| parent | e012cb3783bc2710c5ea9f0c355d5b1715a92174 (diff) | |
| download | bcm5719-llvm-c2a0b13c25c1a44053a2502384b38eaf1813aee1.tar.gz bcm5719-llvm-c2a0b13c25c1a44053a2502384b38eaf1813aee1.zip | |
[AArch64] Add the constraint to NEON scalar mla/mls instructions.
llvm-svn: 193118
| -rw-r--r-- | clang/include/clang/Basic/arm_neon.td | 4 | ||||
| -rw-r--r-- | clang/test/CodeGen/aarch64-neon-intrinsics.c | 16 |
2 files changed, 10 insertions, 10 deletions
diff --git a/clang/include/clang/Basic/arm_neon.td b/clang/include/clang/Basic/arm_neon.td index a748f11a78b..f370bd7de1f 100644 --- a/clang/include/clang/Basic/arm_neon.td +++ b/clang/include/clang/Basic/arm_neon.td @@ -882,11 +882,11 @@ def SCALAR_USQADD : SInst<"vsqadd", "sss", "SUcSUsSUiSUl">; //////////////////////////////////////////////////////////////////////////////// // Signed Saturating Doubling Multiply-Add Long -def SCALAR_SQDMLAL : SInst<"vqdmlal", "rss", "SsSi">; +def SCALAR_SQDMLAL : SInst<"vqdmlal", "rrss", "SsSi">; //////////////////////////////////////////////////////////////////////////////// // Signed Saturating Doubling Multiply-Subtract Long -def SCALAR_SQDMLSL : SInst<"vqdmlsl", "rss", "SsSi">; +def SCALAR_SQDMLSL : SInst<"vqdmlsl", "rrss", "SsSi">; //////////////////////////////////////////////////////////////////////////////// // Signed Saturating Doubling Multiply Long diff --git a/clang/test/CodeGen/aarch64-neon-intrinsics.c b/clang/test/CodeGen/aarch64-neon-intrinsics.c index 1e630ce59a1..1696b49d9b1 100644 --- a/clang/test/CodeGen/aarch64-neon-intrinsics.c +++ b/clang/test/CodeGen/aarch64-neon-intrinsics.c @@ -7226,28 +7226,28 @@ uint64_t test_vsqaddd_u64(uint64_t a, uint64_t b) { return (uint64_t)vsqaddd_u64(a, b); } -int32_t test_vqdmlalh_s16(int16_t a, int16_t b) { +int32_t test_vqdmlalh_s16(int32_t a, int16_t b, int16_t c) { // CHECK: test_vqdmlalh_s16 // CHECK: sqdmlal {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}} - return (int32_t)vqdmlalh_s16(a, b); + return (int32_t)vqdmlalh_s16(a, b, c); } -int64_t test_vqdmlals_s32(int32_t a, int32_t b) { +int64_t test_vqdmlals_s32(int64_t a, int32_t b, int32_t c) { // CHECK: test_vqdmlals_s32 // CHECK: sqdmlal {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} - return (int64_t)vqdmlals_s32(a, b); + return (int64_t)vqdmlals_s32(a, b, c); } -int32_t test_vqdmlslh_s16(int16_t a, int16_t b) { +int32_t test_vqdmlslh_s16(int32_t a, int16_t b, int16_t c) { // CHECK: test_vqdmlslh_s16 // CHECK: sqdmlsl {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}} - return (int32_t)vqdmlslh_s16(a, b); + return (int32_t)vqdmlslh_s16(a, b, c); } -int64_t test_vqdmlsls_s32(int32_t a, int32_t b) { +int64_t test_vqdmlsls_s32(int64_t a, int32_t b, int32_t c) { // CHECK: test_vqdmlsls_s32 // CHECK: sqdmlsl {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} - return (int64_t)vqdmlsls_s32(a, b); + return (int64_t)vqdmlsls_s32(a, b, c); } int32_t test_vqdmullh_s16(int16_t a, int16_t b) { |
