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authorKrzysztof Parzyszek <kparzysz@codeaurora.org>2018-09-18 16:10:51 +0000
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>2018-09-18 16:10:51 +0000
commitc1e2f39b3503869bd471a867c177f6486da5fee0 (patch)
tree3939b44dcee52ee3c8721010db573cc95ce26b85
parent0594162f3238602bc6ae57bc876d27257411df01 (diff)
downloadbcm5719-llvm-c1e2f39b3503869bd471a867c177f6486da5fee0.tar.gz
bcm5719-llvm-c1e2f39b3503869bd471a867c177f6486da5fee0.zip
[PostRASink] Make sure to remove subregisters from live-ins as well
llvm-svn: 342492
-rw-r--r--llvm/lib/CodeGen/MachineSink.cpp7
-rw-r--r--llvm/test/CodeGen/Hexagon/postra-sink-subregs.mir33
2 files changed, 38 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index d52e6198d4e..1d2e85accbc 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -1037,8 +1037,11 @@ static void clearKillFlags(MachineInstr *MI, MachineBasicBlock &CurBB,
static void updateLiveIn(MachineInstr *MI, MachineBasicBlock *SuccBB,
SmallVectorImpl<unsigned> &UsedOpsInCopy,
SmallVectorImpl<unsigned> &DefedRegsInCopy) {
- for (auto DefReg : DefedRegsInCopy)
- SuccBB->removeLiveIn(DefReg);
+ MachineFunction &MF = *SuccBB->getParent();
+ const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
+ for (unsigned DefReg : DefedRegsInCopy)
+ for (MCSubRegIterator S(DefReg, TRI, true); S.isValid(); ++S)
+ SuccBB->removeLiveIn(*S);
for (auto U : UsedOpsInCopy) {
unsigned Reg = MI->getOperand(U).getReg();
if (!SuccBB->isLiveIn(Reg))
diff --git a/llvm/test/CodeGen/Hexagon/postra-sink-subregs.mir b/llvm/test/CodeGen/Hexagon/postra-sink-subregs.mir
new file mode 100644
index 00000000000..0ac13373898
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/postra-sink-subregs.mir
@@ -0,0 +1,33 @@
+# RUN: llc -march=hexagon -run-pass postra-machine-sink,postrapseudos,if-converter -verify-machineinstrs -o - %s | FileCheck %s
+
+# 1. Post-RA machine sinking moves the copy (1) to block %bb.1. The
+# subregisters $r2 and $r3 of $d1 are not removed from the live-ins.
+# 2. Expand post-RA pseudos replaces the COPY with A2_tfrp which is
+# predicable.
+# 3. If-conversion predicates block %bb.1. Since $d1 (made of $r2 and $r3)
+# is in the live-in list to %bb.1, it assumes that $d1 in (1) is live,
+# and adds an implicit use of $d1 to the predicated copy.
+# This results in an invalid machine code, since the implicit use
+# refers to an undefined register.
+
+# Make sure that post-RA machine sinking removes subregisters from live-ins
+# to block bb.1.
+
+# CHECK: $d1 = A2_tfrpf $p0, $d0
+# CHECK-NOT: implicit killed $d1
+
+name: fred
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $d0, $p0
+ renamable $d1 = COPY $d0 ;; (1)
+ J2_jumpt $p0, %bb.2, implicit-def $pc
+ bb.1:
+ liveins: $r2, $r3
+ $r0 = A2_addi $r2, 1
+ bb.2:
+ liveins: $r0
+ A2_nop
+ J2_jumpr $r31, implicit-def $pc
+...
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