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| author | Sanjay Patel <spatel@rotateright.com> | 2018-04-22 15:59:14 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2018-04-22 15:59:14 +0000 |
| commit | c1265ab99e3621d982db8f6070a7ce5a35aab2f1 (patch) | |
| tree | 367f26244d515b9bb841b7623b670bc5acecbe07 | |
| parent | ef8d3ae4b53acda0500878cebba688ae48e41280 (diff) | |
| download | bcm5719-llvm-c1265ab99e3621d982db8f6070a7ce5a35aab2f1.tar.gz bcm5719-llvm-c1265ab99e3621d982db8f6070a7ce5a35aab2f1.zip | |
[InstCombine] add vector test with undef elts; NFC
llvm-svn: 330547
| -rw-r--r-- | llvm/test/Transforms/InstCombine/logical-select.ll | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/llvm/test/Transforms/InstCombine/logical-select.ll b/llvm/test/Transforms/InstCombine/logical-select.ll index d31af5e964a..dd95cc02751 100644 --- a/llvm/test/Transforms/InstCombine/logical-select.ll +++ b/llvm/test/Transforms/InstCombine/logical-select.ll @@ -479,6 +479,19 @@ define <4 x i32> @vec_not_sel_consts(<4 x i32> %a, <4 x i32> %b) { ret <4 x i32> %or } +define <4 x i32> @vec_not_sel_consts_undef_elts(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: @vec_not_sel_consts_undef_elts( +; CHECK-NEXT: [[AND1:%.*]] = and <4 x i32> [[A:%.*]], <i32 -1, i32 undef, i32 0, i32 0> +; CHECK-NEXT: [[AND2:%.*]] = and <4 x i32> [[B:%.*]], <i32 0, i32 -1, i32 0, i32 undef> +; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[AND1]], [[AND2]] +; CHECK-NEXT: ret <4 x i32> [[OR]] +; + %and1 = and <4 x i32> %a, <i32 -1, i32 undef, i32 0, i32 0> + %and2 = and <4 x i32> %b, <i32 0, i32 -1, i32 0, i32 undef> + %or = or <4 x i32> %and1, %and2 + ret <4 x i32> %or +} + ; The inverted constants may be operands of xor instructions. define <4 x i32> @vec_sel_xor(<4 x i32> %a, <4 x i32> %b, <4 x i1> %c) { |
