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| author | Diana Picus <diana.picus@linaro.org> | 2019-02-15 10:50:02 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2019-02-15 10:50:02 +0000 |
| commit | c0f964eb2f191a281d3288dc58bc6dfdc10c4b79 (patch) | |
| tree | caa898f52c7b9d510a56735fd5b1a505627aee15 | |
| parent | 5f54fe2332ef3fcb34e20f5d62e6c2664d065ef1 (diff) | |
| download | bcm5719-llvm-c0f964eb2f191a281d3288dc58bc6dfdc10c4b79.tar.gz bcm5719-llvm-c0f964eb2f191a281d3288dc58bc6dfdc10c4b79.zip | |
[ARM GlobalISel] Style fix. NFCI
Add the opcode for ADDrr / t2ADDrr to the Opcode cache, as we did for
all other opcodes where the handling is otherwise the same between arm
mode and thumb2.
llvm-svn: 354115
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstructionSelector.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp index 3030e219474..0c95c21054d 100644 --- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp +++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp @@ -97,6 +97,8 @@ private: unsigned STORE8; unsigned LOAD8; + unsigned ADDrr; + // Used for G_ICMP unsigned CMPrr; unsigned MOVi; @@ -297,6 +299,8 @@ ARMInstructionSelector::OpcodeCache::OpcodeCache(const ARMSubtarget &STI) { STORE_OPCODE(STORE8, STRBi12); STORE_OPCODE(LOAD8, LDRBi12); + STORE_OPCODE(ADDrr, ADDrr); + STORE_OPCODE(CMPrr, CMPrr); STORE_OPCODE(MOVi, MOVi); STORE_OPCODE(MOVCCi, MOVCCi); @@ -957,7 +961,7 @@ bool ARMInstructionSelector::select(MachineInstr &I, return selectShift(ARM_AM::ShiftOpc::lsl, MIB); } case G_GEP: - I.setDesc(TII.get(STI.isThumb2() ? ARM::t2ADDrr : ARM::ADDrr)); + I.setDesc(TII.get(Opcodes.ADDrr)); MIB.add(predOps(ARMCC::AL)).add(condCodeOp()); break; case G_FRAME_INDEX: |
