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| author | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2019-02-15 19:13:55 +0000 |
|---|---|---|
| committer | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2019-02-15 19:13:55 +0000 |
| commit | c0eef3542b3a045d1a868baff150f2e4f775d3ca (patch) | |
| tree | 2e3c7ea4e562e94b08561fd1efc0cc07c449edfe | |
| parent | 5f5cac3ae29d44869f64d9629d9443656199fc1d (diff) | |
| download | bcm5719-llvm-c0eef3542b3a045d1a868baff150f2e4f775d3ca.tar.gz bcm5719-llvm-c0eef3542b3a045d1a868baff150f2e4f775d3ca.zip | |
Recommit "[SystemZ] Do not emit VEXTEND or VROUND nodes without vector support."
It seems there were some problem with using a .mir test. For some reason
doing '-stop-before=codegenprepare' and then '-start-before=codegenprepare'
on the output .mir file results in the NoVRegs Property after instruction
selection.
Recommitting the same test as an .ll file instead.
llvm-svn: 354160
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/fp-conv-18.ll | 34 |
2 files changed, 42 insertions, 0 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 6bbc4e9fd10..310fd41354e 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -5505,6 +5505,10 @@ SDValue SystemZTargetLowering::combineJOIN_DWORDS( SDValue SystemZTargetLowering::combineFP_ROUND( SDNode *N, DAGCombinerInfo &DCI) const { + + if (!Subtarget.hasVector()) + return SDValue(); + // (fpround (extract_vector_elt X 0)) // (fpround (extract_vector_elt X 1)) -> // (extract_vector_elt (VROUND X) 0) @@ -5552,6 +5556,10 @@ SDValue SystemZTargetLowering::combineFP_ROUND( SDValue SystemZTargetLowering::combineFP_EXTEND( SDNode *N, DAGCombinerInfo &DCI) const { + + if (!Subtarget.hasVector()) + return SDValue(); + // (fpextend (extract_vector_elt X 0)) // (fpextend (extract_vector_elt X 2)) -> // (extract_vector_elt (VEXTEND X) 0) diff --git a/llvm/test/CodeGen/SystemZ/fp-conv-18.ll b/llvm/test/CodeGen/SystemZ/fp-conv-18.ll new file mode 100644 index 00000000000..5ca52effc0f --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/fp-conv-18.ll @@ -0,0 +1,34 @@ +; Test that VEXTEND or VROUND nodes are not emitted without vector support. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s + +; CHECK-LABEL: fun1: +; CHECK: ldeb +; CHECK-LABEL: fun2: +; CHECK: ledbr + +@.str = external dso_local unnamed_addr constant [21 x i8], align 2 + +define void @fun1() #0 { +bb: +%tmp = load <4 x float>, <4 x float>* undef, align 16 +%tmp1 = extractelement <4 x float> %tmp, i32 0 +%tmp2 = fpext float %tmp1 to double +%tmp3 = extractelement <4 x float> %tmp, i32 2 +%tmp4 = fpext float %tmp3 to double +tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([21 x i8], [21 x i8]* @.str, i64 0, i64 0), double %tmp2, double undef, double %tmp4, double undef) +ret void +} + +define void @fun2() #0 { +bb: +%tmp = load <2 x double>, <2 x double>* undef, align 16 +%tmp1 = extractelement <2 x double> %tmp, i32 0 +%tmp2 = fptrunc double %tmp1 to float +%tmp3 = extractelement <2 x double> %tmp, i32 1 +%tmp4 = fptrunc double %tmp3 to float +tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([21 x i8], [21 x i8]* @.str, i64 0, i64 0), float %tmp2, float undef, float %tmp4, float undef) +ret void +} + +declare dso_local void @printf(i8*, ...) #0 |

