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| author | Tim Northover <tnorthover@apple.com> | 2013-05-30 13:56:32 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-05-30 13:56:32 +0000 |
| commit | c0b42a257d64745019465aa3d62785265a8ca144 (patch) | |
| tree | 286e248cda71f31c1a9403713c022e1b87ca553f | |
| parent | 64ec0ff43336cedc5dfae2accb27c0fb6f27f5e7 (diff) | |
| download | bcm5719-llvm-c0b42a257d64745019465aa3d62785265a8ca144.tar.gz bcm5719-llvm-c0b42a257d64745019465aa3d62785265a8ca144.zip | |
X86: allow registers 8-15 in test
This test was failing on some hosts when an unexpected register was used for a
variable. This just extends the regexp to allow the new x86-64 registers.
llvm-svn: 182929
| -rw-r--r-- | llvm/test/CodeGen/X86/zext-sext.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/X86/zext-sext.ll b/llvm/test/CodeGen/X86/zext-sext.ll index e4264aef4c1..2459f1fa254 100644 --- a/llvm/test/CodeGen/X86/zext-sext.ll +++ b/llvm/test/CodeGen/X86/zext-sext.ll @@ -33,9 +33,9 @@ entry: %tmp11 = sext i32 %tmp4 to i64 %tmp12 = add i64 %tmp11, 5089792279245435153 -; CHECK: addl $2138875574, %e[[REGISTER_zext:[a-z]+]] -; CHECK-NEXT: movslq %e[[REGISTER_zext]], [[REGISTER_tmp:%[a-z]+]] -; CHECK: movq [[REGISTER_tmp]], [[REGISTER_sext:%[a-z]+]] +; CHECK: addl $2138875574, %e[[REGISTER_zext:[a-z0-9]+]] +; CHECK-NEXT: movslq %e[[REGISTER_zext]], [[REGISTER_tmp:%r[a-z0-9]+]] +; CHECK: movq [[REGISTER_tmp]], [[REGISTER_sext:%r[a-z0-9]+]] ; CHECK-NEXT: subq %r[[REGISTER_zext]], [[REGISTER_sext]] %tmp13 = sub i64 %tmp12, 2138875574 |
