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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-03-25 20:43:01 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-03-25 20:43:01 +0000 |
| commit | c0720a40526a634cac1e472cfdf0721732ad1857 (patch) | |
| tree | cb5a535c60e19f97a150fb71918d33f5e11b8ea1 | |
| parent | 0935875c40b33e80c17c3fcf489c3aa2aa5ef1d6 (diff) | |
| download | bcm5719-llvm-c0720a40526a634cac1e472cfdf0721732ad1857.tar.gz bcm5719-llvm-c0720a40526a634cac1e472cfdf0721732ad1857.zip | |
[X86][SSE] Combine (VSRLI (VSRAI X, Y), (NumSignBits-1)) -> (VSRLI X, (NumSignBits-1))
Part 3 of 3.
Differential Revision: https://reviews.llvm.org/D31347
llvm-svn: 298782
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/combine-and.ll | 1 |
2 files changed, 9 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 547250375aa..02e39dadea7 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -31075,13 +31075,14 @@ static SDValue combineVectorShift(SDNode *N, SelectionDAG &DAG, bool LogicalShift = X86ISD::VSHLI == Opcode || X86ISD::VSRLI == Opcode; EVT VT = N->getValueType(0); SDValue N0 = N->getOperand(0); + SDValue N1 = N->getOperand(1); unsigned NumBitsPerElt = VT.getScalarSizeInBits(); assert(VT == N0.getValueType() && (NumBitsPerElt % 8) == 0 && "Unexpected value type"); // Out of range logical bit shifts are guaranteed to be zero. // Out of range arithmetic bit shifts splat the sign bit. - APInt ShiftVal = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); + APInt ShiftVal = cast<ConstantSDNode>(N1)->getAPIntValue(); if (ShiftVal.zextOrTrunc(8).uge(NumBitsPerElt)) { if (LogicalShift) return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, SDLoc(N)); @@ -31097,6 +31098,13 @@ static SDValue combineVectorShift(SDNode *N, SelectionDAG &DAG, if (ISD::isBuildVectorAllZeros(N0.getNode())) return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, SDLoc(N)); + // fold (VSRLI (VSRAI X, Y), 31) -> (VSRLI X, 31). + // This VSRLI only looks at the sign bit, which is unmodified by VSRAI. + // TODO - support other sra opcodes as needed. + if (Opcode == X86ISD::VSRLI && (ShiftVal + 1) == NumBitsPerElt && + N0.getOpcode() == X86ISD::VSRAI) + return DAG.getNode(X86ISD::VSRLI, SDLoc(N), VT, N0.getOperand(0), N1); + // We can decode 'whole byte' logical bit shifts as shuffles. if (LogicalShift && (ShiftVal.getZExtValue() % 8) == 0) { SDValue Op(N, 0); diff --git a/llvm/test/CodeGen/X86/combine-and.ll b/llvm/test/CodeGen/X86/combine-and.ll index 352705b48d9..f30fa61bbfb 100644 --- a/llvm/test/CodeGen/X86/combine-and.ll +++ b/llvm/test/CodeGen/X86/combine-and.ll @@ -253,7 +253,6 @@ define <4 x i32> @and_or_zext_v4i16(<4 x i16> %a0) { define <8 x i16> @ashr_mask1_v8i16(<8 x i16> %a0) { ; CHECK-LABEL: ashr_mask1_v8i16: ; CHECK: # BB#0: -; CHECK-NEXT: psraw $15, %xmm0 ; CHECK-NEXT: psrlw $15, %xmm0 ; CHECK-NEXT: retq %1 = ashr <8 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> |
