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| author | Craig Topper <craig.topper@intel.com> | 2017-10-02 00:44:50 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-10-02 00:44:50 +0000 |
| commit | c05c390a7cf89e7cf3a06586a44a39b88369fa12 (patch) | |
| tree | 267979895fc42a7a3817f2a8caf20fe1b63bdabc | |
| parent | 9bcdd80b66d45242599343c2a78ab7806662feff (diff) | |
| download | bcm5719-llvm-c05c390a7cf89e7cf3a06586a44a39b88369fa12.tar.gz bcm5719-llvm-c05c390a7cf89e7cf3a06586a44a39b88369fa12.zip | |
[X86] Use _NOREX MOVZX instructions for some patterns even in 32-bit mode.
This unifies the patterns between both modes. This should be effectively NFC since all the available registers in 32-bit mode statisfy this constraint.
llvm-svn: 314643
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrCompiler.td | 38 |
1 files changed, 6 insertions, 32 deletions
diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td index ec560a6e3ce..6f7a8d3817c 100644 --- a/llvm/lib/Target/X86/X86InstrCompiler.td +++ b/llvm/lib/Target/X86/X86InstrCompiler.td @@ -1488,21 +1488,16 @@ def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), Requires<[Not64BitMode]>; def : Pat<(srl GR16:$src, (i8 8)), (EXTRACT_SUBREG - (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), - sub_16bit)>, - Requires<[Not64BitMode]>; + (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), + sub_16bit)>; def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), - (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>, - Requires<[Not64BitMode]>; + (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), - (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>, - Requires<[Not64BitMode]>; + (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), - (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>, - Requires<[Not64BitMode]>; + (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), - (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>, - Requires<[Not64BitMode]>; + (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; // h-register tricks. // For now, be conservative on x86-64 and use an h-register extract only if the @@ -1518,27 +1513,6 @@ def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi)), sub_32bit)>; -def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), - (MOVZX32_NOREXrr8 - (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>, - Requires<[In64BitMode]>; -def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), - (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>, - Requires<[In64BitMode]>; -def : Pat<(srl GR16:$src, (i8 8)), - (EXTRACT_SUBREG - (MOVZX32_NOREXrr8 - (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), - sub_16bit)>, - Requires<[In64BitMode]>; -def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), - (MOVZX32_NOREXrr8 - (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>, - Requires<[In64BitMode]>; -def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), - (MOVZX32_NOREXrr8 - (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>, - Requires<[In64BitMode]>; def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), (SUBREG_TO_REG (i64 0), |
