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authorBob Wilson <bob.wilson@apple.com>2010-08-14 03:18:29 +0000
committerBob Wilson <bob.wilson@apple.com>2010-08-14 03:18:29 +0000
commitbffc757df713fb1799d389a309a1c7192bb13c0c (patch)
tree967df6b1b93ce4f8418ca767eaf47ffcc560ebf9
parentdf2392572e1d538e49585ba3459ad37a89d22a35 (diff)
downloadbcm5719-llvm-bffc757df713fb1799d389a309a1c7192bb13c0c.tar.gz
bcm5719-llvm-bffc757df713fb1799d389a309a1c7192bb13c0c.zip
T2I_rbin_irs rr variant is for disassembly only, so don't provide a pattern.
llvm-svn: 111068
-rw-r--r--llvm/lib/Target/ARM/ARMInstrThumb2.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index 16b7cb41f34..1e8d80aed29 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -275,7 +275,7 @@ multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
// register
def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, rGPR:$lhs), IIC_iALUr,
opc, "\t$dst, $rhs, $lhs",
- [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
+ [/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
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