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author | Karthik Bhat <kv.bhat@samsung.com> | 2014-12-22 13:38:58 +0000 |
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committer | Karthik Bhat <kv.bhat@samsung.com> | 2014-12-22 13:38:58 +0000 |
commit | bf662901c1c7d94e23c359468ebca5e5e059419c (patch) | |
tree | 830e88fe6c26028575c0060702cad9558d568375 | |
parent | 2645d33977bc6692c1d646289d99bcddf2eb1237 (diff) | |
download | bcm5719-llvm-bf662901c1c7d94e23c359468ebca5e5e059419c.tar.gz bcm5719-llvm-bf662901c1c7d94e23c359468ebca5e5e059419c.zip |
Lower multiply-negate operation to mneg on AArch64
This patch pattern matches code such as-
neg w8, w8
mul w8, w9, w8
to
mneg w8, w8, w9
Review: http://reviews.llvm.org/D6754
llvm-svn: 224706
-rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.td | 4 | ||||
-rw-r--r-- | llvm/test/CodeGen/AArch64/dp-3source.ll | 15 |
2 files changed, 19 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 01a01e059a5..3f1dbe0bfc0 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -657,6 +657,10 @@ def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))), (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>; def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))), (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>; +def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)), + (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>; +def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)), + (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>; } // AddedComplexity = 7 let AddedComplexity = 5 in { diff --git a/llvm/test/CodeGen/AArch64/dp-3source.ll b/llvm/test/CodeGen/AArch64/dp-3source.ll index 22bd4a844e1..bd96ec728f5 100644 --- a/llvm/test/CodeGen/AArch64/dp-3source.ll +++ b/llvm/test/CodeGen/AArch64/dp-3source.ll @@ -161,3 +161,18 @@ define i64 @test_umnegl(i32 %lhs, i32 %rhs) { ; CHECK: umnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ret i64 %res } + +@a = common global i32 0, align 4 +@b = common global i32 0, align 4 +@c = common global i32 0, align 4 + +define void @test_mneg(){ +; CHECK-LABEL: test_mneg: + %1 = load i32* @a, align 4 + %2 = load i32* @b, align 4 + %3 = sub i32 0, %1 + %4 = mul i32 %2, %3 + store i32 %4, i32* @c, align 4 +; CHECK: mneg {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + ret void +} |