Mips specific inline assembler constraint 'R'

'R' An address that can be sued in a non-macro load or store.

Including missing positive test case and fixed typo for r176453.

Thanks to Richard Smith for catching this!

Jack

llvm-svn: 176506

2 files changed, 27 insertions, 1 deletions

diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index a433cc70be8..5a15145d2e1 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -4487,7 +4487,7 @@ public:
     case 'x': // hilo register pair
       Info.setAllowsRegister();
       return true;
-    case 'R': // An address tha can be used in a non-macro load or store
+    case 'R': // An address that can be used in a non-macro load or store
       Info.setAllowsMemory();
       return true;
     }
diff --git a/clang/test/CodeGen/mips-constraints-mem.c b/clang/test/CodeGen/mips-constraints-mem.c
new file mode 100644
index 00000000000..ea6bcaff973
--- /dev/null
+++ b/clang/test/CodeGen/mips-constraints-mem.c
@@ -0,0 +1,26 @@
+// RUN: %clang -target mipsel-unknown-linux -S -o - -emit-llvm %s \
+// RUN: | FileCheck %s
+
+// This checks that the frontend will accept inline asm memory constraints.
+
+int foo()
+{
+
+ // 'R': An address that can be used in a non-macro load or stor'
+ // This test will result in the higher and lower nibbles being
+ // switched due to the lwl/lwr instruction pairs.
+ // CHECK:   %{{[0-9]+}} = call i32 asm sideeffect  "lwl $0, 1 + $1\0A\09lwr $0, 2 + $1\0A\09", "=r,*R"(i32* %{{[0-9,a-f]+}}) #1, !srcloc !0
+
+  int c = 0xffbbccdd;
+
+  int *p = &c;
+  int out = 0;
+
+  __asm volatile (
+    "lwl %0, 1 + %1\n\t"
+    "lwr %0, 2 + %1\n\t"
+    : "=r"(out)
+    : "R"(*p)
+    );
+  return 0;
+}