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authorMatt Arsenault <Matthew.Arsenault@amd.com>2019-03-25 21:10:12 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2019-03-25 21:10:12 +0000
commitbc978872dea88b238a37b45a81e3866e7094d8e9 (patch)
treeb144e6daa983084d7187fc9618be4d76d035982a
parentfdce82a814c05b1f89ae50c494845b27ec043891 (diff)
downloadbcm5719-llvm-bc978872dea88b238a37b45a81e3866e7094d8e9.tar.gz
bcm5719-llvm-bc978872dea88b238a37b45a81e3866e7094d8e9.zip
AMDGPU: Set hasSideEffects 0 on _term instructions
These were defaulting to true, but they are just wrappers around bit operations. This avoids regressions in the exec mask optimization passes in a future commit. llvm-svn: 356952
-rw-r--r--llvm/lib/Target/AMDGPU/SIInstructions.td3
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 869deb93679..b0ab7032d97 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -172,12 +172,14 @@ def S_MOV_B64_term : SPseudoInstSI<(outs SReg_64:$dst),
(ins SSrc_b64:$src0)> {
let isAsCheapAsAMove = 1;
let isTerminator = 1;
+ let hasSideEffects = 0;
}
def S_XOR_B64_term : SPseudoInstSI<(outs SReg_64:$dst),
(ins SSrc_b64:$src0, SSrc_b64:$src1)> {
let isAsCheapAsAMove = 1;
let isTerminator = 1;
+ let hasSideEffects = 0;
let Defs = [SCC];
}
@@ -185,6 +187,7 @@ def S_ANDN2_B64_term : SPseudoInstSI<(outs SReg_64:$dst),
(ins SSrc_b64:$src0, SSrc_b64:$src1)> {
let isAsCheapAsAMove = 1;
let isTerminator = 1;
+ let hasSideEffects = 0;
}
def WAVE_BARRIER : SPseudoInstSI<(outs), (ins),
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