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| author | Aditya Nandakumar <aditya_nandakumar@apple.com> | 2017-03-22 01:16:39 +0000 |
|---|---|---|
| committer | Aditya Nandakumar <aditya_nandakumar@apple.com> | 2017-03-22 01:16:39 +0000 |
| commit | bc389badbc45288b0050c4b323374f1c0243fdf3 (patch) | |
| tree | 022ea822ad366dcf7a29c77c1442691ffbec0700 | |
| parent | 0498baa4bea05471f7e683e460e20fd7c5cd6293 (diff) | |
| download | bcm5719-llvm-bc389badbc45288b0050c4b323374f1c0243fdf3.tar.gz bcm5719-llvm-bc389badbc45288b0050c4b323374f1c0243fdf3.zip | |
[GlobalISel]: Create VREGs for ConstantInt args
This patch changes the behavior of IRTranslating intrinsics where we
now create VREG + G_CONSTANT for ConstantInt values. We already do this
for FloatingPoint values. This makes it easier for the backends to
select code and it won't have to de-duplicate creation+selection of
constants.
Reviewed by: ab
llvm-svn: 298473
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 5 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll | 3 |
2 files changed, 3 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index b3f131b5eeb..76618737844 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -772,10 +772,7 @@ bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) { // Some intrinsics take metadata parameters. Reject them. if (isa<MetadataAsValue>(Arg)) return false; - if (ConstantInt *CI = dyn_cast<ConstantInt>(Arg)) - MIB.addImm(CI->getSExtValue()); - else - MIB.addUse(getOrCreateVReg(*Arg)); + MIB.addUse(getOrCreateVReg(*Arg)); } return true; } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index d837968ed2e..4356168d5d8 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -488,7 +488,8 @@ define void @store(i64* %addr, i64 addrspace(42)* %addr42, i64 %val1, i64 %val2) ; CHECK-LABEL: name: intrinsics ; CHECK: [[CUR:%[0-9]+]](s32) = COPY %w0 ; CHECK: [[BITS:%[0-9]+]](s32) = COPY %w1 -; CHECK: [[PTR:%[0-9]+]](p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0 +; CHECK: [[CREG:%[0-9]+]](s32) = G_CONSTANT i32 0 +; CHECK: [[PTR:%[0-9]+]](p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), [[CREG]] ; CHECK: [[PTR_VEC:%[0-9]+]](p0) = G_FRAME_INDEX %stack.0.ptr.vec ; CHECK: [[VEC:%[0-9]+]](<8 x s8>) = G_LOAD [[PTR_VEC]] ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), [[VEC]](<8 x s8>), [[VEC]](<8 x s8>), [[PTR]](p0) |
