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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-08-31 18:46:07 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-08-31 18:46:07 +0000 |
| commit | ba5730884bf0cb345f03bedc4a8fce3f13b9962a (patch) | |
| tree | 3071568c00cc47e77e2534d834f9c4b14cbbb737 | |
| parent | 1c06a73a7c300105e9f685d4388e0f2d6c0021a1 (diff) | |
| download | bcm5719-llvm-ba5730884bf0cb345f03bedc4a8fce3f13b9962a.tar.gz bcm5719-llvm-ba5730884bf0cb345f03bedc4a8fce3f13b9962a.zip | |
AMDGPU/SI: Make sure llvm.amdgcn.implicitarg.ptr() is at least 4-byte aligned
Summary: This fixes some OpenCV tests that were broken by libclc commit r276443.
Reviewers: arsenm, jvesely
Subscribers: arsenm, wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D24051
llvm-svn: 280274
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll | 14 |
2 files changed, 15 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 11f31563924..32e40a2c7a7 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -2683,7 +2683,7 @@ SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG, uint32_t AMDGPUTargetLowering::getImplicitParameterOffset( const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const { - uint64_t ArgOffset = MFI->getABIArgOffset(); + uint64_t ArgOffset = alignTo(MFI->getABIArgOffset(), 4); switch (Param) { case GRID_DIM: return ArgOffset; diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll index 07650d990f3..41977c286f3 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll @@ -27,6 +27,20 @@ define void @test_implicit(i32 addrspace(1)* %out) #1 { ret void } +; ALL-LABEL: {{^}}test_implicit_alignment +; MESA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc +; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3 +; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]] +; MESA: buffer_store_dword [[V_VAL]] +; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]] +define void @test_implicit_alignment(i32 addrspace(1)* %out, <2 x i8> %in) #1 { + %implicitarg.ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() + %arg.ptr = bitcast i8 addrspace(2)* %implicitarg.ptr to i32 addrspace(2)* + %val = load i32, i32 addrspace(2)* %arg.ptr + store i32 %val, i32 addrspace(1)* %out + ret void +} + declare i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #0 declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() #0 |
