[X86] Allow base and index for gather instructions to appear in other order for Intel syntax.

llvm-svn: 335500

2 files changed, 16 insertions, 0 deletions

diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index ac322263130..a7dbdee5243 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1883,6 +1883,17 @@ std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() {
       (IndexReg == X86::ESP || IndexReg == X86::RSP))
     std::swap(BaseReg, IndexReg);
 
+  // If BaseReg is a vector register and IndexReg is not, swap them unless
+  // Scale was specified in which case it would be an error.
+  if (Scale == 0 &&
+      !(X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||
+        X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||
+        X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg)) &&
+      (X86MCRegisterClasses[X86::VR128XRegClassID].contains(BaseReg) ||
+       X86MCRegisterClasses[X86::VR256XRegClassID].contains(BaseReg) ||
+       X86MCRegisterClasses[X86::VR512RegClassID].contains(BaseReg)))
+    std::swap(BaseReg, IndexReg);
+
   if (Scale != 0 &&
       X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg))
     return ErrorOperand(Start, "16-bit addresses cannot have a scale");
diff --git a/llvm/test/MC/X86/intel-syntax.s b/llvm/test/MC/X86/intel-syntax.s
index 72f18def389..428a7e4ec41 100644
--- a/llvm/test/MC/X86/intel-syntax.s
+++ b/llvm/test/MC/X86/intel-syntax.s
@@ -897,3 +897,8 @@ lea rax, [rsp+rax]
 lea eax, [eax+esp]
 // CHECK: leal (%esp,%eax), %eax
 lea eax, [esp+eax]
+
+// CHECK: vpgatherdq      %ymm2, (%rdi,%xmm1), %ymm0
+vpgatherdq ymm0, [rdi+xmm1], ymm2
+// CHECK: vpgatherdq      %ymm2, (%rdi,%xmm1), %ymm0
+vpgatherdq ymm0, [xmm1+rdi], ymm2